EP80579 Datasheet, PDF (978/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
26.2
Warning:
Note:
USB 2.0 PCI Configuration Registers
The default values are defined with an h for hex, a b for binary, or 00 for zero. If there
is not a letter following the default value, assume it is a binary number.
Address locations that are not listed are considered reserved registers locations. Reads
to reserved registers may return non-zero values. Writes to reserved locations may
cause system failure.
Reserved bits are Read Only.
Table 26-2. Bus 0, Device 29, Function 7: Summary of USB (2.0) Controller PCI
Configuration Registers (Sheet 1 of 2)
Offset Start Offset End
Register ID - Description
Default
Value
00h
02h
04h
06h
08h
09h
0Ah
0Bh
0Dh
10h
2Ch
2Eh
34h
3Ch
3Dh
50h
51h
52h
54h
58h
59h
5Ah
60h
61h
62h
64h
68h
6Ch
01h
03h
05h
07h
08h
09h
0Ah
0Bh
0Dh
13h
2Dh
2Fh
34h
3Ch
3Dh
50h
51h
53h
55h
58h
59h
5Bh
60h
61h
63h
65h
6Bh
6Fh
“Offset 00h: VID - Vendor ID Register” on page 979
8086h
“Offset 02h: DID - Device Identification Register” on page 979
5035h
“Offset 04h: CMD - Command Register” on page 980
0000h
“Offset 06h: DSR - Device Status Register” on page 981
0290h
“Offset 08h: RID - Revision ID Register” on page 983
Variable
“Offset 09h: PI - Programming Interface Register” on page 983
20h
“Offset 0Ah: SCC - Sub Class Code Register” on page 983
03h
“Offset 0Bh: BCC - Base Class Code Register” on page 984
0Ch
“Offset 0Dh: MLT - Master Latency Timer Register” on page 984
00h
“Offset 10h: MBAR - Memory Base Address Register” on page 985
00000000h
“Offset 2Ch: SSVID - USB 2.0 Subsystem Vendor ID Register” on page 985
XXXXh
“Offset 2Eh: SSID - USB 2.0 Subsystem ID Register” on page 986
XXXXh
“Offset 34h: CAP_PTR - Capabilities Pointer Register” on page 986
50h
“Offset 3Ch: ILINE - Interrupt Line Register” on page 987
00h
“Offset 3Dh: IPIN - Interrupt Pin Register” on page 987
Variable
“Offset 50h: PM_CID - PCI Power Management Capability ID Register” on page 987 01h
“Offset 51h: PM_NEXT - Next Item Pointer #1 Register” on page 988
58h
“Offset 52h: PM_CAP - Power Management Capabilities Register” on page 989
C9C2h
“Offset 54h: PM_CS - Power Management Control/Status Register” on page 990 0000h
“Offset 58h: DP_CID - Debug Port Capability ID Register” on page 991
0Ah
“Offset 59h: DP_NEXT - Next Item Pointer #2 Register” on page 991
00h
“Offset 5Ah: DP_BASE - Debug Port Base Offset Register” on page 991
20A0h
“Offset 60h: SBRN - Serial Bus Release Number Register” on page 992
20h
“Offset 61h: FLA - Frame Length Adjustment Register” on page 992
20h
“Offset 62h: PWC - Port Wake Capability Register” on page 993
01FFh
“Offset 64h: CUO - Classic USB Override Register” on page 994
0000h
“Offset 68h: ULSEC - USB 2.0 Legacy Support Extended Capability Register” on
page 994
00000001h
“Offset 6Ch: ULSCS - USB 2.0 Legacy Support Control/Status Register” on
page 995
00000000h
Intel^® EP80579 Integrated Processor Product Line Datasheet
978
August 2009
Order Number: 320066-003US