EP80579 Datasheet, PDF (135/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
In this table, “:” and “via” indicates bridged and direct paths for the signaling (see
Figure 4-2), respectively. All EP80579 hardware that inter-operates with IA platform
structures for signaling, such as the signal bridge, operate in IA physical address space.
This allows it to access IA platform devices, such as the LAPIC that are accessed via
MMIO reads and writes in the PCI L memory region.
The next two sections cover the various signaling scenarios that are represented in the
cells of Table 4-1: signaling that travels around the bridge and that is bridged from a
side band signal.
4.3.1
Signaling that Travels Around the Signal Bridge
For signaling that does not need to travel through the signal bridge, the EP80579 does
not require any specific signaling support. In these cases, the signaling occurs over an
existing path. For example, an interrupt from a IICH USB controller would travel over
the existing IICH INTx or MSI path based on device configuration.
4.3.2
Signaling that is Bridged from a Side-Band Source Signal
The majority of signaling scenarios in Table 4-1 that require bridging are conversions
between side band signals and a signal that targets the IA-32 core. The EP80579 uses
a centralized agent, the signal bridge to perform this conversion. One or more side-
band signals arrive at the signal bridge from each AIOC device that is capable of
signaling. The bridge is responsible for generating the appropriate outbound signal to
either an ASU device or the IA-32 core. Figure 4-3 presents an overview of the signal
bridge hardware for a subset of the EP80579 AIOC devices.
Figure 4-3. Signal Bridging
AIOC
n
AIOC
n
GbE 0
n
AIOC
n
Signal Bridge
MSI
0 mar C, mdr Z
9 mar ?, mdr ?
10 mar A, mdr X
11
INTb
Signal Target
mask M₀, data ?
mask M₉, data S
mask M₁₀, data ?
mask M₁₁, data ?
INT<n>
MSI [C], f(Z)
ASU
IA
Logically, the signal bridge consists of the MSI and Signal Target capability records from
the PCI configuration headers for the AIOC devices. The MSI capability record for a
device includes a message address register (mar in Figure 4-3) and Message data
register (mdr in Figure 4-3) that indicate the address and data for the MSI as per the
PCI definition of this capability. The Signal Target capability record for a device includes
a mask that determines how the bridge steers the signal, data which identifies
additional signaling data, and a status that indicates which side-band signal(s) has
been asserted¹. The Signal Target capability is a vendor-specific capability record
whose format the EP80579 defines.
In the example show in Figure 4-3, side band signals arrive from Gigabit Ethernet MAC
and other AIOC agents. These agents correspond to AIOC PCI devices. Here, the GbE
agent generates a signal that the signal bridge delivers as an MSI to IA based on the
1. The status is not shown in Figure 4-3.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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