EP80579 Datasheet, PDF (1462/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.3.6
Note:
ICR1 – Interrupt 1 Cause Read Register
This register contains all interrupt conditions for the GbE. Whenever an interrupt
causing event occurs, the corresponding interrupt bit is set in this register. See “IMS0 –
Interrupt 0 Mask Set/Read Register” on page 1459 for additional details.
All register bits clear on read. Thus, reading this register implicitly acknowledges all
pending interrupt events. Writing a 1 to any bit in the register will also clear that bit.
Writing a 0 to any bit will have no effect.
Table 37-42. ICR1: Interrupt 1Cause Read Register (Sheet 1 of 3)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 08C0h
Offset End: 08C3h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 08C0h
Offset End: 08C3h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 08C0h
Offset End: 08C3h
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range
31 : 29
28
27
26
25 : 24
23
22
Bit Acronym
Bit Description
Sticky
RSVD
Reserved
ERR_INTBUS
Internal Bus Error.
This bit indicates that an error occurred during either a
Target or Host transaction on the bus. Refer to Section
37.5.12, “Error Handling” for complete details.
The details of this error are reported in the
INTBUS_ERR_STAT register.
ERR_STAT
Statistic Register ECC Error. The Statistic Registers are
implemented using a memory that uses a single-bit
correct/multi-bit detect ECC parity algorithm to protect it.
This bit indicates that a multi-bit error has occurred on a
read from that memory. No indication of a single-bit error
correction will be given by hardware.
Note: If this interrupt asserts, further GbE DMA Reads
and Writes are blocked until software issues a soft
reset to the GbE by writing the Device Control
Register (CTRL.RST)
ERR_MCFSPF
Multicast Filter Parity Error/Special Packet Filter
Parity Error. The Multicast Filter and Special Packets Filter
use parity protected SRAMs for data buffers. This bit
indicates that a parity error has occurred on a read from
either of these data buffers. This error is considered non-
fatal and will clear after a read of the MEM_ERR_STAT
register.
RSVD
Reserved
ERR_PB
DMA Packet Buffer 2-bit ECC Error. The 64KB DMA
Packet Buffer uses a single-bit correct/multi-bit detect ECC
parity algorithm to protect the SRAM it uses for data. This
bit indicates that a multi-bit error has occurred on a read
from that SRAM. No indication of a single-bit error
correction will be given by hardware.
Note: If this interrupt asserts, further GbE DMA Reads
and Writes are blocked until software issues a soft
reset to the GbE by writing the Device Control
Register (CTRL.RST).
RSVD
Reserved
Bit Reset
Value
0h
0h
0h
0h
0h
0h
0h
Bit Access
RV
RCWC
RCWC
RCWC
RV
RCWC
RV
Intel^® EP80579 Integrated Processor Product Line Datasheet
1462
August 2009
Order Number: 320066-003US