EP80579 Datasheet, PDF (538/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.4.1.17 Offset 20h: MBASE - Memory Base Address Register
This register controls the processor to PCI Express* non-prefetchable memory access
routing based on the following formula:
MEMORY_BASE =< address =< MEMORY_LIMIT
Note:
The upper 12 bits of the register are read/write and correspond to the upper 12
address bits A[31:20] of the 32-bit address. The bottom four bits of this register are
read-only and return zeroes when read. This register must be initialized by the
configuration software. For the purpose of address decode address bits A[19:00] of the
Memory Base Address are assumed to be 0. Similarly, the bridge assumes that the
lower 20 bits of the Memory Limit Address (A[19:00]) are F_FFFFh. Thus, the bottom of
the defined memory address range are aligned to a 1 Mbyte boundary, and the top of
the defined memory range is at the top of a 1 Mbyte memory block. Memory range
covered by MBASE and MLIMIT registers are used to map non-prefetchable PCI
Express* address ranges (typically where control/status memory-mapped I/O data
structures of the graphics controller resides) and PMBASE and PMLIMIT are used to
map prefetchable address ranges (typically graphics local memory). This segregation
allows application of USWC space attribute to be performed in a true plug-and-play
manner to the prefetchable address range for improved PCI Express* memory access
performance.
Configuration software is responsible for programming all address range registers
(prefetchable, non-prefetchable) with the values that provide exclusive address ranges
(for example, to prevent overlap with each other and/or with the ranges covered with
the main memory). There is no provision in the CMI hardware to enforce prevention of
overlap and operations of the system in the case of overlap are not guaranteed.
Table 16-156.Offset 20h: MBASE - Memory Base Address Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 20h
Offset End: 21h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 20h
Offset End: 21h
Size: 16 bit
Default: FFF0h
Power Well: Core
Bit Range
15 : 04
03 : 00
Bit Acronym
Bit Description
Sticky
MBASE
Reserved
Memory Address Base: Corresponds to A[31:20] of the
lower limit of the memory range that are passed by the
Device 2 bridge to PCI Express*.
Reserved
Bit Reset
Value
FFFh
0h
Bit Access
RW
16.4.1.18 Offset 22h: MLIMIT - Memory Limit Address Register
This register controls the processor to PCI Express* non-prefetchable memory access
routing based on the following formula:
MEMORY_BASE =< address =< MEMORY_LIMIT
Intel^® EP80579 Integrated Processor Product Line Datasheet
538
August 2009
Order Number: 320066-003US