EP80579 Datasheet, PDF (1489/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.4.16 RAH[0-15] – Receive Address High Register
These registers contain the upper bits of the 48 bit Ethernet address. The complete 48b
address is {RAH, RAL}. The first receive address register (RAR0) is also used for exact
match pause frame checking (i.e. the destination address matches the first register).
Therefore RAR0 should always be used to store the individual Ethernet MAC address of
the adapter.
Table 37-65. RAH[0-15] - Receive Address High Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 5404h at 8h
Offset End: 5407h at 8h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 5404h at 8h
Offset End: 5407h at 8h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 5404h at 8h
Offset End: 5407h at 8h
Size: 32 bits
Default: 000XXXXXh
Power
Well:
GbE0: Aux
2: Core
Gbe1/
Bit Range
31
30 : 18
17 : 16
15 : 00
Bit Acronym
Bit Description
Sticky
AV
Rsvd
ASEL
RAH
Address valid. This bit determines whether this address
is compared against the incoming packet. Cleared after
software reset or Unit Reset.
0 = No match on this address field
1 = Match on this address field
Reserved
Address Select. Selects how the address is to be used
when performing special filtering on receive packets.
• 00: Destination address (must be set to this in
normal mode)
• 01: Source address
• 10: Reserved
• 11: Reserved
Receive Address High. The upper 16 bits of the 48 bit
Ethernet address.
Bit Reset
Value
0h
0h
X
X
Bit Access
RW
RV
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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