EP80579 Datasheet, PDF (1681/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Figure 42-5. Expansion Bus I/O Wait Operation
T1
T2
(1Cycle) (1 Cycle)
EX_CLK
T3
(3 Cycles)
T4
T5
(1 Cycle) (1 Cycle)
EX_CS_N
EX_ADDR
EX_IOWAIT_N
EX_RD_N
EX_DATA
valid address
valid data
42.4.1.5
42.4.1.6
Parity
The Expansion bus controller generates even or odd parity for each byte written to
EX_DATA and compares parity for each byte read on EX_DATA, if PAR_EN is set in each
EXP_TIMING_CS register. EX_PARITY is transferred in the same clock cycle in which
EX_DATA is transferred. If a read transfer results in a parity mismatch on EX_PARITY,
the target address is logged in the EXP_PARITY_STATUS and OutErrorSts is set.
Exp_parity_error will be asserted by the Expansion bus controller during a parity error
and an interrupt will be generated if enabled in the interrupt controller.
Exp_parity_error will remain asserted until software clears EXP_PARITY_STATUS
register.
Even parity is defined as the number of 1’s on EX_DATA[7:0] and EX_PARITY[0] must
be an even number. For example, if EX_DATA[7:0] = 0x25, EX_PARITY[0] must be 1,
since there are 3 bits set on 0x25 and there needs to be an even number of 1s. Parity
for the second byte of EX_DATA is generated on EX_PARITY[1].
If PAR_EN is cleared for a particular device, the Expansion bus controller doesn’t
generate or compare parity and EX_PARITY should not toggle to conserve power. Odd
parity can be enabled by setting OddPar in the EXP_MST_CONTROL register and is
equivalent to the inverted value of even parity.
Special Design Knowledge for Using HPI mode
The Expansion bus controller supports a number of the 8-bit and 16-bit versions of the
Texas Instruments Host Port Interface* (HPI) standards. This flexibility allows the
TMS320C54xx family of Digital Signals Processors (DSP) to seamlessly interface to the
Expansion Bus.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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