EP80579 Datasheet, PDF (1026/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
6. The ADE does not fetch data when a QH is encountered in the Ping state. An Ack
handshake in response to the Ping results in the ADE writing the QH to the Out
state, which results in the fetching and delivery of the Out Data on the next
iteration through the asynchronous list.
7. The ADE will not pipeline fetch a Queue Head if the other transaction slot contains
that Queue Head already (i.e., only one active QH). This is to avoid executing based
on stale fields in the Queue Head since a status write (or overlay) is expected to
occur following execution of the pending transaction. The ADE will traverse the
schedule (any inactive Queue Heads) before encountering the Link Pointer to the
stale structure. At that point the fetching pauses until the pending transaction is
completed.
8. Once the ADE checks the length of an asynchronous packet against the remaining
time in the microframe (late-start check) and decides that there is not enough time
to run it on the wire, then the EHC stops all activity on the USB ports for the
remainder of that microframe. The EHC does not attempt to look for any shorter
packets in the remainder of the asynchronous schedule that might be able to fit in
the current microframe. Unlike the PDE, the ADE keeps the transaction internally
for executing in the next microframe without refetching from memory.
9. An entry in the 2-deep command FIFO becomes available for a new transaction
fetch when any of the following events occur:
a. The final transaction results are posted in write buffers to memory.
b. A host error causes an unexpected halt. Any unexecuted transactions in the
command FIFO are flushed.
10. Once the ADE detects an “empty” asynchronous schedule as described in the EHCI
Specification, it implements a waking mechanism like the one in the example. The
amount of time that the ADE “sleeps” is 10 µs +/-30 ns.
11. Data fetches are not initiated unless there is room in the Out Data FIFO for the
amount of data requested.
12. Read requests are broken up and throttled based on the Read Request Maximum
Length field and the Request Rate Throttle fields in the configuration register at
offset FCh. Control or Data structures that cross a Maximum Length-aligned
boundary in memory are broken into multiple requests. This allows other packets
from within the IICH to be interleaved on the IMCH/IICH link and through the
memory controller to avoid temporary starvation of those functions. When
generating the multiple read requests, the EHC will naturally-align the requests
(i.e., 64-byte requests will not fetch across 64-byte address boundaries in
memory). This guarantees that, as cache-line sizes increase, the back-to-back
requests do not cause double-snoops on specific cache lines. Unlike control
structure read requests, only reads for data will be subject to the Request Rate
Throttle.
13. Periodic DMA memory accesses may be interleaved at any point with the
asynchronous DMA memory accesses on IMCH/IICH link.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1026
August 2009
Order Number: 320066-003US