EP80579 Datasheet, PDF (614/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-236.Offset A0h: DQSFAIL0 - DQS Failure Configuration Register 0
Description: DQSFAIL0: DQS Failure Configuration Register
View: PCI
BAR: SMRBASE
Bus:Device:Function: 0:0:0
Offset Start: A0h
Offset End: A3h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range Bit Acronym
5
Reserved_R0DQ
S11
Reserved
4
R0DQS02 Rank 0 DQS02
3
Reserved_R0DQ
S10
Reserved
2
R0DQS01 Rank 0 DQS01
1
Reserved_R0DQ
S09
Reserved
0
R0DQS00 Rank 0 DQS00
Bit Description
Sticky
Bit Reset
Value
Bit Access
Y
0b
RW
Y
0b
RW
Y
0b
RW
Y
0b
RW
Y
0b
RW
Y
0b
RW
16.5.1.10 DRRTC: Receive Enable Reference Output Timing Control Registers
Note:
These registers have to be saved and restored on S3.
The DRRTC is a set of three registers with DQS receiver enable window timing control
for each byte on the DDR data bus. There is a single control for each byte for both
ranks. A correct register setting will delay the start of the enable window so that it
coincides with the middle of the DQS pre-amble. Enabling the window before or after
the pre-amble would cause valid DQS edges to be missed or invalid edges or noise to
be received.
The range of the enable delay, controlled by the DRRTC registers, is eight cycles, with a
granularity defined by the DDRIOMC2.MASTCNTL register (controls setting for the
Master DLL). The delay is measured from the memory controller clock edge that
launches a “read” command on the DDR command bus. The minimum delay is equal to
the DDR SDRAM read latency defined in the DRT0.CL register field. The maximum delay
is the read latency plus eight cycles. In order words the DRRTC registers can introduce
up to 8 cycles of delay. This DRRTC delay does not included the contributions of CL and
registered DIMM to the total read latency. In addition to these major sources of delay,
there is also a small “uncompensated delay” as shown in the formulas below.
The RCVEN fields of the DRRTC register control the delay as follows: bits [7:5] control
whole clock increments, bits [4:3] control in quarter clock increments, and bits [2:0]
control the sub-quarter cycle increments. Setting RCVEN to 0x0 produces the minimum
delay, and 0xFF sets the maximum delay. The sub-quarter cycle delay is defined by the
equations and “RCVEN_OUT” lookup table below:
Delay_Uncomp = 100ps; Note: estimate only
Delay Element = (quarter CMDCLK period - Delay_Uncomp) / (MASTCNTL + 0.5)
sub quarter cycle delay = Delay_Uncomp + (Delay Element * RCVEN_OUT[2:0])
Intel^® EP80579 Integrated Processor Product Line Datasheet
614
August 2009
Order Number: 320066-003US