EP80579 Datasheet, PDF (75/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
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UART Register/Signal Reset States ...................................................................1174
Summary of UART Registers in I/O Space (DLAB=0) ............................................1175
Summary of UART Registers in I/O Space (DLAB=1) ............................................1175
Summary of UART Timer registers in I/O space ...................................................1175
Internal Register Descriptions ..........................................................................1176
Offset 00h: RBR - Receive Buffer Register ........................................................1176
Offset 00h: THR - Transmit Holding Register .....................................................1177
Offset 01h: IER - Interrupt Enable Register .......................................................1177
Interrupt Conditions .......................................................................................1178
Offset 02h: IIR - Interrupt Identification Register ..............................................1179
Interrupt Identification Register Decode ............................................................1179
Offset 02h: FCR - FIFO Control Register ...........................................................1180
Offset 03h: LCR - Line Control Register ............................................................1182
Offset 04h: MCR - Modem Control Register .......................................................1184
Offset 05h: LSR - Line Status Register .............................................................1186
Offset 06h: MSR - Modem Status Register ........................................................1189
Offset 07h: SCR - Scratchpad Register .............................................................1190
Offset 00h: DLL - Programmable Baud Rate Generator Divisor Latch Register Low .1190
Offset 01h: DLH - Programmable Baud Rate Generator Divisor Latch Register High .1190
Summary of Watchdog Timer Registers in I/O Space............................................1194
Offset 00h: PV1R0 - Preload Value 1 Register 0 .................................................1194
Offset 01h: PV1R1 - Preload Value 1 Register 1 .................................................1195
Offset 02h: PV1R2 - Preload Value 1 Register 2 .................................................1195
Offset 04h: PV2R0 - Preload Value 2 Register 0 .................................................1196
Offset 05h: PV2R1 - Preload Value 2 Register 1 .................................................1196
Offset 06h: PV2R2 - Preload Value 2 Register 2 .................................................1197
Offset 08h: GISR - General Interrupt Status Register .........................................1197
Offset 0Ch: RR0 - Reload Register 0 ................................................................1198
Offset 0Dh: RR1 - Reload Register 1 ................................................................1199
Offset 10h: WDTCR - WDT Configuration Register ..............................................1199
Offset 18h: WDTLR - WDT Lock Register ..........................................................1201
SIW_SERIRQ Sampling Periods ........................................................................1204
Configuration Register Summary ......................................................................1207
Logical Device 4 (Serial Port 1) ........................................................................1210
Logical Device 5 (Serial Port 2) ........................................................................1211
Logical Device 6 (Watch Dog Timer) .................................................................1212
Bus 0, Device 4, Function 0: Summary of PCI-to-PCI Bridge PCI
Configuration Registers ....................................................................................1215
PCI-to-PCI Bridge PCI Header .........................................................................1216
Offset 0h: VID: Vendor Identification Register ...................................................1217
Offset 2h: DID: Device Identification Register ...................................................1217
Offset 4h: PCICMD: Device Command Register ..................................................1217
Offset 6h: PCISTS: PCI Device Status Register ..................................................1218
Offset 8h: RID: Revision ID Register ................................................................1219
Offset 9h: CC: Class Code Register ..................................................................1219
Offset Ch: CLS: Cacheline Size Register ...........................................................1219
Offset Dh: LT: Latency Timer Register ..............................................................1220
Offset Eh: HDR: Header Type Register .............................................................1220
Offset 10h: CSRBAR0: Control and Status Registers Base Address Register ...........1220
Offset 14h: CSRBAR1: Control and Status Registers Base Address Register ...........1221
Offset 18h: PBNUM: Primary Bus Number Register .............................................1221
Offset 19h: SECBNM: Secondary Bus Number Register .......................................1221
Offset 1Ah: SUBBNM: Subordinate Bus Number Register ....................................1222
Offset 1Bh: SECLT: Secondary Latency Timer Register .......................................1222
Offset 1Ch: IOB: I/O Base Register ..................................................................1222
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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