EP80579 Datasheet, PDF (1059/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
27.3.3.3 Offset 04h: PM1_CNT - Power Management 1 Control Register
Table 27-13. Offset 04h: PM1_CNT - Power Management 1 Control Register
Description:
View: PCI
Size: 32 bit
BAR: PMBASE (IO)
Default: 0000h
Bus:Device:Function: 0:31:0
Offset Start: 04h
Offset End: 04h
Power Well: Core^a
Bit Range
31 : 14
13
Bit Acronym
Bit Description
Sticky
Reserved
SLP_EN
Reserved
This is a write-only bit and reads to it always return a
zero. Setting this bit causes the system to sequence into
the Sleep state defined by the SLP_TYP field.
This 3-bit field defines the type of Sleep the system
must enter when the SLP_EN bit is set to 1. These bits
are reset by RTEST# only.
Bit Reset
Value
0h
0h
Bit Access
WO
12 : 10
SLP_TYP
Bits
Mode
Typical
Mapping
000 ON
S0
Just assert STPCLK#. Puts
processor in Stop-Grant state.
001 ^{Can also assert CPUSLP#, to}
S1
put processor in Sleep state.
010 Reserved
011 Reserved
100 Reserved
101 Suspend-To-RAM
S3
Suspend-To-Disk
110
S4
111 Soft Off
S5
0h
RW
09 : 03
02
00
Reserved
GBL_RLS
Reserved
SCI_EN
Reserved
This bit is used by the ACPI software to raise an event to
the BIOS software. BIOS software has a corresponding
enable and status bits to control its ability to receive
ACPI events. This bit always reads as 0.
Reserved
Selects the SCI interrupt or the SMI# for various
events.
0 = These events generate an SMI#.
1 = The events generate an SCI interrupt.
a. Bits 0-7: Core, Bits 8-12: RTC, Bits 13-15: Resume
0h
0h
WO
0h
0h
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1059