EP80579 Datasheet, PDF (1607/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
40.4.1 SSP Control Register 0
40.4.1.1 Offset 00h: SSCR0 - SSP Control Register 0 Details
The SSP control register 0 (SSCR0) contains five different bit fields that control various
functions within the SSP.
Register Name:
SSCR0
Block
Base Address:
N/A
Offset Address
00
Reset Value
00000000
Register Description: SSC Control Register 0
Access: (See below.)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
SCR
FRF
SRS
Table 40-2. Offset 00h: SSCR0 - SSP Control Register 0 Details (Sheet 1 of 2)
Description: SSP Control Register 0
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:6:0
Offset Start: 00h
Offset End: 03h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 :16
15 :08
7
Bit Acronym
Bit Description
Sticky
Reserved
SCR
SSE
Reserved
Serial Clock Rate Selection
Value (0 to 255) used to generate transmission rate of
SSP.
Bit rate = CLK/ (2 x (SCR + 1)) where SCR is a decimal
integer
CLK may be the internally provided clock of 3.7
MHz (2.777MHz for low-power SKU) or the externally
provided clock.
Synchronous Serial Port Enable bit.
0 = SSP operation disabled
1 = SSP operation enabled
Bit Reset
Value
0h
0h
0b
Bit Access
RV
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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