EP80579 Datasheet, PDF (611/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.5.1.6
Offset 94h: RCVENAC - Receiver Enable Algorithm Control Register
This register contains controls for the preamble detection algorithm of the automatic
receiver enable logic. RCVENAC.PWIDTH is used to determine if a “low” pulse in a DQS
waveform is wide enough to be a preamble. RCVENAC.POFFSET is subtracted from the
DCALDATA first edge position result and programmed into the DRRTC registers
Table 16-233.Offset 94h: RCVENAC - Receiver Enable Algorithm Control Register
Description: RCVENAC: Receiver Enable Algorithm Control
View: PCI
BAR: SMRBASE
Bus:Device:Function: 0:0:0
Offset Start: 94h
Offset End: 96h
Size: 24 bit
Default: 180810h
Power Well: Core
Bit Range
23 :16
15 :14
13 :08
7 :06
5 :00
Bit Acronym
Bit Description
Sticky
Minimum preamble width limit, used to detect if a low
PWIDTH
pulse in a DQS waveform is wide enough to be a valid
preamble. The default corresponds to 3/4 of a DRAM clock
Y
cycle
Reserved Reserved
Minimum high pulse width limit, used to detect if a
HWIDTH
high pulse in a DQS waveform is wide enough to indicate a
strobe is toggling in a valid manner. The default
Y
corresponds to 1/4 of a DRAM clock cycle.
Reserved Reserved
Preamble center offset from first rising edge, used to
POFFSET
position the DQS receiver enable relative to the preamble
edge location recorded in the DCALDATA registers. The
Y
default value corresponds to 1/2 of a DRAM clock cycle.
Bit Reset
Value
18h
00b
08h
00b
10h
Bit Access
RW
RO
RW
RO
RW
16.5.1.7
Offset 98h: DSRETC - DRAM Self-Refresh (SR) Extended Timing and
Control
This register implements bits fields that control self-refresh entry and exit mechanisms
that are required for ACPI S3 mode of operation.
Table 16-234.Offset 98h: DSRETC - DRAM Self-Refresh (SR) Extended Timing and Control
Register
Description: DSRETC: DRAM Self-Refresh (SR) Extended Timing and Control Register
View: PCI
BAR: SMRBASE
Bus:Device:Function: 0:0:0
Offset Start: 98h
Offset End: 9Bh
Size: 32 bit
Default: 5c141400h
Power Well: Core
Bit Range
31 :24
23 :16
Bit Acronym
Bit Description
Sticky
TXSNR
Exit self-refresh to non-read command timing. Number of
Controller cycles for which accesses to the DIMMs need to Y
be blocked by memory controller.
Dual rank self-refresh (SR) entry and exit timing - stagger
of self refresh commands between ranks.
DRSRENT
Staggering of the SR commands result is in the power
intensive refresh operations to be staggered between the
Y
2 ranks.
Bit Reset
Value
01011100b
00010100b
Bit Access
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
611