EP80579 Datasheet, PDF (409/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-26. Offset 9Ch: DEVPRES - Device Present Register (Sheet 2 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 9Ch
Offset End: 9Ch
Size: 8 bit
Default: 33h
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
0 = PCI Express port A is disabled.
02
Device_2_Prese 1 = PCI Express port A is enabled.When the SKU value is
nt
cleared, this field is read/write. When the SKU value is set,
this field becomes a read-only ‘0’
01
Device_1_Prese 0 = EDMA Controller is disabled.
nt
1 = EDMA Controller is enabled.
00
Reserved Reserved
Bit Reset
Value
0b
1b
1b
Bit Access
RWO or RO
RWO
16.1.1.25 Offset 9Dh: EXSMRC - Extended System Management RAM Control
Register
The Extended SMRAM register controls the configuration of Extended SMRAM space.
The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM
memory space that is above 1 MByte.
Table 16-27. Offset 9Dh: EXSMRC - Extended System Management RAM Control Register
(Sheet 1 of 3)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 9Dh
Offset End: 9Dh
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07
Bit Acronym
Bit Description
Sticky
H_SMRAME
Enable High SMRAM: Controls the SMM memory space
location (above 1 MByte or below 1 MByte)
0 = High SMRAM memory space is disabled.
1 = And G_SMRAME is 1, the high SMRAM memory space
is enabled.
SMRAM accesses within the range 0FEDA_0000h to
0FEDB_FFFFh are remapped to DRAM addresses within the
range 000A0000h to 000BFFFFh. Once D_LCK (See
Table 35) has been set, this bit becomes Read-Only.
Bit Reset
Value
0b
Bit Access
RWL
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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