EP80579 Datasheet, PDF (1052/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 27-5. Offset A4h: GEN_PMCON_3 - General PM Configuration 3 Register (Sheet 2 of
2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:0
Offset Start: A4h
Offset End: A4h
Size: 8 bit
Default: 00h
Power Well: RTC
Bit Range
01
00
Bit Acronym
Bit Description
Sticky
PWR_FLR
AG3E
PWR_FLR:
0 = Indicates that the trickle current has not failed since
the last time the bit was cleared.
1 = Indicates that the trickle current (from the main
battery or trickle supply) was removed or failed.
Software writes a 1 to this bit to clear it. This bit is in
the RTC well, and is not cleared by any type of reset
except RTEST#.
Notes:
1.
RSMRST# is sampled using the RTC clock.
Therefore, low times that are less than one RTC
clock period may not be detected.
2.
Clearing CMOS in CMI platforms can be done by
using a jumper on RTEST# or GPI.
Implementations must not attempt to clear CMOS
by using a jumper to pull VccRTC low.
AFTERG3_EN: Determines what state to go to when
power is reapplied after a power failure (G3 state).
0 = System will return to an S0 state (boot) after power is
reapplied.
1 = System will return to the S5 state (except if it was in
S4, in which case it will return to S4-like state).
In addition to software writes, this bit is set by the
following hardware conditions:
• Power Button Override
• SMBus Unconditional Powerdown Message
• Catastrophic Temperature condition from an internal
sensor
• Assertion of CPU Thermal Trip input
Bit Reset
Value
0h
0h
Bit Access
RWC
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1052
August 2009
Order Number: 320066-003US