EP80579 Datasheet, PDF (1536/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.7.3
WUS – Wake Up Status Register (0x05810; RW)
This register is used to record statistics about all Wake Up packets received. If a packet
matches multiple criteria than multiple bits could be set. Writing a 1 to any bit will clear
that bit.
This register will not be cleared when RESET_N is asserted. It will only be cleared when
PWR_OK is deasserted or when cleared by the driver.
Prior to re-entering a wakeup-enabled sleep state, this register should be explicitly
cleared by writing with all 1's.
Table 37-133.WUS - Wake Up Status Register (0x05810; RW)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 5810h
Offset End: 5813h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 5810h
Offset End: 5813h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 5810h
Offset End: 5813h
Size: 32 bits
Default: 00000000h
Power
Well:
GbE0: Aux
Gbe1/2: Core
Bit Range
31 : 20
19
18
17
16
15 : 08
07
06
05
04
03
02
01
00
Bit Acronym
Bit Description
Sticky
RSVD
FLX3
FLX2
FLX1
FLX0
Reserved
IPV6
IPV4
ARP
BC
MC
EX
MAG
Rsvd
Reserved. Should be set to 0.
Flexible Filter 3 Match
Flexible Filter 2 Match
Flexible Filter 1 Match
Flexible Filter 0 Match
Reserved.
Directed IPv6 Packet Wake Up Packet Received
Directed IPv4 Packet Wake Up Packet Received
ARP/IPv4 Request Packet Wake Up Packet Received
Broadcast Wake Up Packet Received
Directed Multicast Wake Up Packet Received
The packet was a multicast packet whose hashed to a
value that corresponded to a 1 bit in the Multicast Table
Array
Note: If the MAC has been configured for promiscuous
mode, a multicast wakeup will occur if a broadcast
packet is received. This is because a broadcast
message is a special type of multicast message.
Refer to 802.3.
Directed Exact Wake Up Packet Received
The packet's address matched one of the 16 pre-
programmed exact values in the Receive Address registers
Magic Packet Wake Up Packet Received
Reserved. Must be written as ‘0’
Bit Reset
Value
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
Bit Access
RV
RWC
RWC
RWC
RWC
RV
RWC
RWC
RWC
RWC
RWC
RWC
RWC
RV
Intel^® EP80579 Integrated Processor Product Line Datasheet
1536
August 2009
Order Number: 320066-003US