EP80579 Datasheet, PDF (1849/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 49-21. PCI Express* Differential Transmitter (TX) Specifications (Sheet 2 of 2)
Symbol
Parameter
Min
Nom Max
Unit Figures Notes
V_{TX-CM-DC- Absolute Delta of DC Common Mode}
ACTIVE-IDLE- _{Voltage During L0 and Electrical Idle}
0
DELTA
V_TX-CM-DC- Absolute Delta of DC Common Mode
LINE-DELTA ^{Voltage between D+ and D–}
0
V_TX-IDLE-
DIFFp
Electrical Idle Differential Peak
Output Voltage
0
V_TX-RCV-
DETECT
The amount of voltage change
allowed during Receiver Detection
T_{TX_IDLE- Minimum time spent in Electrical Idle}
50
MIN
T_TX-IDLE-
SET-TO-IDLE
Maximum time to transition to a valid
Electrical Idle after sending an
Electrical Idle ordered set
100
mV
-
8
20
mV
8
20
mV
8
600
mV
12
UI
20
UI
T_TX-IDLE-TO-
Maximum time to transition to valid
Tx Specification after leaving an
DIFF-DATA _{Electrical Idle condition}
20
UI
T_TX-IDLE-
RCV-DETECT-
MAX
Maximum time spent in electrical
Idle before initiating a receiver
detect sequence
100
ms
12
RL_TX-DIFF Differential Return Loss
10
dB
10
RL_TX-CM Common Mode Return Loss
6
dB
10
T_crosslink Crosslink Random Timeout
0
1
ms
Notes:
1.
Specified at the measurement point into a timing and voltage compliance test load as shown in
Figure 49-14 and measured over any 250 consecutive Unit Intervals. Also refer to the Transmitter
Compliance Eye Diagram as shown in Figure 49-15.
2.
The allowed DC Common Mode voltage under any conditions. Refer to Section 4.3.1.8 in the PCI-
Express* Specification for further details.
3.
Static skew between any two Transmitter Lanes within a single link
4.
The allowed current when any output is shorted to ground.
5.
PCI-Express mVdiff p-p = PEx_Xp[x] - PEx_Xn[x]
6.
Guaranteed by design. These values are typical values seen for this process, but not measured during
production testing.
7.
No test load is necessarily associated with this value.
8.
Specified at the measurement point into a timing and voltage compliance test load as shown in
Figure 49-14 and measured over any 250 consecutive Unit Intervals. Also refer to the Transmitter
Compliance Eye Diagram as shown in Figure 49-16.
9.
A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTX-
JITTER-MAX = 0.30 UI for the transmitter collected over any 250 consecutive Tx UIs. The TTX-EYE-
MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median and the
maximum deviation from the median is less than half of the total Tx jitter budget collected over any
250 consecutive Tx UIs. Note that the median is not the same as the mean. The jitter median
describes the point in time where the number of jitter points on either side is approximately equal, as
opposed to the average value.
10.
The transmitter input impedance shall result in a differential return loss greater than or equal to 12
dB and a common mode return loss greater than 6 dB over a frequency range of 50 MHz to 1.25 GHz.
This input impedance requirement applies to all valid input levels. The reference impedance for return
less measurements is 50 Ω to ground for both the D+ and D– line (for example, as measured by a
Vector Network Analyzer with 50 Ω probes – see Figure 49-16). Note that the series capacitors CTX is
optional for the return loss measurement.
11.
Measured between 20–80% at Transmitter package pins into a test load as shown in Figure 49-16 for
both VTX-D+ and VTX-D–.
12.
Refer to Section 4.3.1.8 in the PCI-Express* Specification for further details.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1849