EP80579 Datasheet, PDF (1202/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
33.6.3
33.6.3.1
33.6.3.2
Note:
33.6.3.3
33.6.3.4
Theory Of Operation
RTC Well and WDT_TOUT# Functionality
The WDT_TIMEOUT bit is set to a ‘1’ when the WDT 35-bit down counter reaches zero
for the second time in a row. Then the WDT_TOUT# pin is toggled LOW by the WDT
from the IICH. The board designer must attach the WDT_TOUT# to the appropriate
external signal. If WDT_TOUT_CNF is a ‘1’ the WDT toggles WDT_TOUT# again the
next time a time out occurs. Otherwise WDT_TOUT# is driven low until the system is
reset or power is cycled.
Register Unlocking Sequence
The register unlocking sequence is necessary whenever writing to the RELOAD register
or either PRELOAD_VALUE registers. The host must write a sequence of two writes to
offset BAR1 + 0Ch before attempting to write to either the WDT_RELOAD and
WDT_TIMEOUT bits of the RELOAD register or the PRELOAD_VALUE registers. The first
writes are “80” and “86” (in that order) to offset BAR1 + 0Ch. The next write is to the
proper memory mapped register (e.g., RELOAD, PRELOAD_VALUE_1,
PRELOAD_VALUE_2). Any deviation from the sequence (writes to memory-mapped
registers) causes the host to have to restart the sequence.
When performing register unlocking, software must issue the cycles using byte access
only. Otherwise the unlocking sequence will not work properly.
The following is an example of how to prevent a timeout:
1. Write “80” to offset BAR1 + 0Ch.
2. Write “86” to offset BAR1 + 0Ch.
3. Write a ‘1’ to RELOAD [8] (WDT_RELOAD) of the Reload Register.
Any subsequent writes require that this sequence be performed again.
Reload Sequence
To keep the timer from causing an interrupt or driving WDT_TOUT#, the timer must be
updated periodically. Other timers refer to “updating the timer” as “kicking the timer”.
The frequency of updates required is dependent on the value of the Preload values. To
update the timer the Register Unlocking Sequence must be performed followed by
writing a ‘1’ to bit 8 at offset BAR1 + 0Ch within the watchdog timer memory mapped
space. This sequence of events is referred to as the “Reload Sequence”.
Low Power State
The Watchdog Timer does not operate when PCICLK is stopped.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1202
August 2009
Order Number: 320066-003US