EP80579 Datasheet, PDF (497/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.2.1.55 Offset C8h: DRAM_SECN_ADD - DRAM Next Single Bit Error Correct
Address Register
Captures the address of the next SEC error (either normal or scrub read) occurring in
the memory system. The value in this register is only valid if the Correctable Read
Memory Error bit(bit 0) in the DRAM_NERR register (see Section 16.2.1.37, “Offset
82h: DRAM_NERR - DRAM Next Error Register”) has been set. The bits in this register
are sticky through reset.
Table 16-109.Offset C8h: DRAM_SECN_ADD - DRAM Next Single Bit Error Correct Address
Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: C8h
Offset End: CBh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31
30 :02
01 :00
Bit Acronym
Bit Description
Sticky
Reserved Reserved
Next Correctable Error Address: This field contains
system address bits 35:12 for the next correctable error.
RETRADD
This field is set by hardware when the Correctable Read
Memory Error bit in the DRAM_SERR register is set. This
Y
value represents a physical address. This field can only be
reset by a PWRGD reset.
Reserved Reserved
Bit Reset
Value
0b
0000000h
0b
Bit Access
RO
RO
RO
16.2.1.56 Offset DCh: RANKTHREX - Rank Error Threshold Exceeded Register
Preserves knowledge of DIMM error thresholds exceeded on a per-rank basis. Software
writes bits individually to 1 to clear them. Hardware sets these bits when the count of
SEC or DED errors transitions from being less than or equal to the defined threshold
value (see the threshold registers such as Section 16.2.1.52, “Offset C2h:
THRESH_DED - DED Error Threshold Register” on page 495) to being greater than the
threshold value for a particular rank. This threshold exceeded bit is cleared by software
and is only rearmed once the threshold is not exceeded. In other words, if the
threshold count has been exceeded and the count is still greater than the threshold,
then when software clears a given indicator bit, this same bit is not automatically set
again until rearmed by the time decay of the error count and the threshold exceeded
event occurs again. The bits in this register are sticky through reset.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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