EP80579 Datasheet, PDF (860/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.3.3.5 Offset 110h: PxIS[0-1] – Port [0-1] Interrupt Status Register
Table 23-60. Offset 110h: PxIS[0-1] – Port [0-1] Interrupt Status Register (Sheet 1 of 2)
Description:
View: PCI
BAR: ABAR
Bus:Device:Function: 0:31:2
Offset Start: 110h, 190h
Offset End: 113h, 193h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31
30
29
28
27
26
25
24
23
22
21 : 08
07
06
05
Bit Acronym
Bit Description
Sticky
CPDS
TFES
HBFS
HBDS
IFS
INFS
Reserved
OFS
Reserved
PRCS
Reserved
DIS
PCS
DPS
Cold Port Detect Status (CPDS): The SATA controller
does not support cold presence detect.
Task File Error Status (TFES): This bit is set whenever
the status register is updated by the device and the error
bit (bit 0) is set.
Host Bus Fatal Error Status (HBFS): Indicates that the
HBA encountered a host bus error that it cannot recover
from, such as a bad software pointer. In PCI, such an
indication would be a target or master abort.
Host Bus Data Error Status (HBDS): Indicates that the
HBA encountered a data error (uncorrectable ECC / parity)
when reading from or writing to system memory.
Interface Fatal Error Status (IFS): Indicates that the
HBA encountered an error on the SATA interface which
caused the transfer to stop.
Interface Non-fatal Error Status (INFS): Indicates
that the HBA encountered an error on the SATA interface
but was able to continue operation.
Reserved
Overflow Status (OFS): Indicates that the HBA received
more bytes from a device than was specified in the PRD
table for the command.
Reserved.
PhyRdy Change Status (PRCS): When set to one
indicates the internal PhyRdy signal changed state. This
bit reflects the state of PxSERR.DIAG.N. This bit is RO and
is only cleared when PxSERR.DIAG.N is cleared.
Note that the internal PhyRdy signal also transitions when
the port interface enters PARTIAL or SLUMBER power
management states. PARTIAL and SLUMBER must be
disabled when Surprise Removal Notification is desired,
otherwise the power management state transitions will
appear as false insertion and removal events.
Reserved
Device Interlock Status (DIS): When set, indicates
that a platform interlock switch has been opened or
closed, which may lead to a change in the connection
state of the device. This bit is only valid in systems that
support an interlock switch (HCAP.SIS set).
For systems that do not support an interlock switch, this
bit will always be ‘0’.
Port Connect Change Status (PCS): 1=Change in
Current Connect Status. 0=No change in Current Connect
Status. This bit reflects the state of PxSERR.DIAG.X. This
bit is only cleared when PxSERR.DIAG.X is cleared.
Descriptor Processed (DPS): A PRD with the ‘I’ bit set
has transferred all of its data.
Bit Reset
Value
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
Bit Access
RO
RWC
RWC
RWC
RWC
RWC
RO
RWC
RWC
RO
RO
RWC
RO
RWC
Intel^® EP80579 Integrated Processor Product Line Datasheet
860
August 2009
Order Number: 320066-003US