EP80579 Datasheet, PDF (810/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 22-6. Offset 0Ch: GP_LVL1 - GPIO Level 1 for Input or Output {31:0} Register
(Sheet 2 of 2)
Description:
This register allows
when output.
reading
of
the
current
GPIO
bit
values
for
GPIO
pins
31-0
when
input,
and
writing
the
value
View: PCI
BAR: GBA(IO)
Bus:Device:Function: 0:31:0
Offset Start: 0Ch
Offset End: 0Fh
Size: 32 bit
Default: FF3F0000h
Power Well: Core^a
Bit Range
22
Bit Acronym
Bit Description
Reserved ^{Reserved. No corresponding GPIO.}
Sticky
Bit Reset
Value
0h
Bit Access
RW
21 : 16
15 : 00
These bits can be updated by software to drive a high or
low value on the output pin when used as GPIO
functions.
GP_LVL_21_16
0=
1=
Low
High
The corresponding GPIO pins are input when used as
IRQ. These bits correspond to GPIOs that are in the core
well and are reset to their native function by PLTRST#.
Reserved Reserved.
a. Core for 0:7, 16:21, 23; Resume for 8:15, 24:31.
3Fh
RW
0000h
RO
22.2.1.4 Offset 18h: GPO_BLINK - GPIO Blink Enable Register
Table 22-7. Offset 18h: GPO_BLINK - GPIO Blink Enable Register (Sheet 1 of 2)
Description:
View: PCI
Size: 32 bit
BAR: GBA(IO)
Default: 00040000h
Bus:Device:Function: 0:31:0
Offset Start: 18h
Offset End: 1Bh
Power Well: Core^a
Bit Range
31 :29
28 : 27
26
Bit Acronym
Bit Description
Sticky
Reserved Reserved.
The setting of this bit has no effect if the corresponding
GPIO signal is programmed as an input.
0 = The corresponding GPIO functions normally.
1 = If the corresponding GPIO is programmed as an
output, the output signal blinks at a rate of
approximately once per second. The high and low
times have approximately 0.5 seconds each. The
GP_LVL bit is not altered when this bit is set.
GPO_BLINK_28 ^{The usage model for a blinking output is to control an}
_27
LED. This value does not need to have exactly one
second granularity, but must be close.
The value of the corresponding GP_LVL bit remains
unchanged during the blink process, and does not effect
the blink in any way.
The GP_LVL bit is not altered when programmed to
blink. It remains at its previous value.
These bits correspond to GPIO in the Resume well and
are reset to their native function by RSMRST# or a write
to the CF9h register or any other PLTRST#
Reserved Reserved.
Bit Reset
Value
0h
00b
0h
Bit Access
RO
RW
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
810
August 2009
Order Number: 320066-003US