EP80579 Datasheet, PDF (233/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 7-54. Bus M, Device 1, Function 0: Summary of Gigabit Ethernet Interface Registers
Mapped Through CSRBAR Memory BAR (Sheet 1 of 4)
Offset Start Offset End
Register ID - Description
0000h
0008h
0018h
00E0h
0010h
0014h
0028h
002Ch
0030h
0038h
0170h
1000h
00C0h
00C4h
00C8h
00D0h
00D8h
08C0h
08C8h
08D0h
08D8h
08E0h
08E8h
08F0h
08F8h
0100h
2160h
2168h
2800h
2804h
2808h
2810h
2818h
2820h
2828h
282Ch
0003h
000Bh
001Bh
00E3h
0013h
0017h
002Bh
002Fh
0033h
003Bh
0173h
1003h
00C3h
00C7h
00CBh
00D3h
00DBh
08C3h
08CBh
08D3h
08DBh
08E3h
08EBh
08F3h
08FBh
0103h
2163h
216Bh
2803h
2807h
280Bh
2813h
281Bh
2823h
282Bh
282Fh
“CTRL: Device Control Register” on page 1438
“STATUS: Device Status Register” on page 1441
“CTRL_EXT: Extended Device Control Register” on page 1442
“CTRL_AUX: Auxiliary Device Control Register” on page 1444
“EEPROM_CTRL - EEPROM Control Register” on page 1446
“EEPROM_RR – EEPROM Read Register” on page 1448
“FCAL: Flow Control Address Low Register” on page 1449
“FCAH: Flow Control Address High Register” on page 1450
“FCT: Flow Control Type Register” on page 1451
“VET: VLAN EtherType Register” on page 1452
“FCTTV: Flow Control Transmit Timer Value Register” on page 1452
“PBA: Packet Buffer Allocation Register” on page 1453
“ICR0: Interrupt 0 Cause Read Register” on page 1454
“ITR0: Interrupt 0 Throttling Register” on page 1457
“ICS0: Interrupt 0 Cause Set Register” on page 1458
“IMS0: Interrupt 0 Mask Set/Read Register” on page 1459
“IMC0: Interrupt 0 Mask Clear Register” on page 1460
“ICR1: Interrupt 1Cause Read Register” on page 1462
“ICS1: Interrupt 0 Cause Set Register” on page 1464
“IMS1: Interrupt 1 Mask Set/Read Register” on page 1466
“IMC1: Interrupt 1 Mask Clear Register” on page 1467
“ICR2: Error Interrupt Cause Read Register” on page 1469
“ICS2: Error Interrupt Cause Set Register” on page 1471
“IMS2: Error Interrupt Mask Set/Read Register” on page 1472
“IMC2: Error Interrupt Mask Clear Register” on page 1473
“RCTL: Receive Control Register” on page 1474
“FCRTL: Flow Control Receive Threshold Low Register” on page 1478
“FCRTH: Flow Control Receive Threshold High Register” on page 1479
“RDBAL: Receive Descriptor Base Address Low Register” on page 1480
“RDBAH: Receive Descriptor Base Address High Register” on page 1480
“RDLEN: Receive Descriptor Length Register” on page 1481
“RDH: Receive Descriptor Head Register” on page 1481
“RDT: Receive Descriptor Tail Register” on page 1482
“RDTR: RX Interrupt Delay Timer (Packet Timer) Register” on page 1483
“RXDCTL: Receive Descriptor Control Register” on page 1483
“RADV: Receive Interrupt Absolute Delay Timer Register” on page 1485
Default
Value
00000A09h
0000XXXXh
00000000h
00000100h
00000X1Xh
XXXXXX00h
00c28001h
00000100h
00008808h
00008100h
00000000h
00100030h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
XXXXXXX0h
XXXXXXXXh
00000000h
00000000h
00000000h
00000000h
00010000h
00000000h
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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