EP80579 Datasheet, PDF (19/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
17.1.6.1
17.1.6.2
17.1.6.3
17.1.6.4
17.1.6.5
17.1.6.6
Offset 3400h: RC - RTC Configuration Register ................................... 704
Offset 3404h: HPTC - High Performance Precision Timer Configuration
Register ........................................................................................ 705
Offset 3410h: GCS: General Control and Status Register...................... 706
Offset 3414h: BUC - Backed Up Control Register................................. 708
Offset 3418h: FD - Function Disable Register...................................... 709
Offset 341Ch: PRC - Power Reduction Control Register Clock
Gating........................................................................................... 711
18.0 System Management ............................................................................................. 713
18.1 Overview ....................................................................................................... 713
18.2 TCO I/O-Mapped Configuration Register Details ................................................... 714
18.2.1 TCO PCI Configuration Registers .............................................................. 715
18.2.2 Bus 0, Device 31, Function 0: TCO Configuration Register (I/O-Mapped via ABASE
BAR) Summary Table ............................................................................. 715
18.2.2.1
18.2.2.2
18.2.2.3
18.2.2.4
18.2.2.5
18.2.2.6
18.2.2.7
18.2.2.8
18.2.2.9
18.2.2.10
18.2.2.11
Offset 00h: TRLD - TCO Timer Reload and Current Value Register ......... 715
Offset 02h: TDI - TCO Data In Register.............................................. 715
Offset 03h: TDO - TCO Data Out Register .......................................... 716
Offset 04h: TSTS1 - TCO 1 Status Register ........................................ 716
Offset 06h: TSTS2 - TCO 2 STS Register ............................................ 718
Offset 08h: TCTL1 - TCO 1 Control Register........................................ 720
Offset 0Ah: TCTL2 - TCO 2 Control Register ....................................... 721
Offset 0Ch: TMSG[1-2] - TCO MESSAGE Register ................................ 721
Offset 0Eh: TWDS - TCO Watchdog Status Register ............................. 722
Offset 10h: LE - Legacy Elimination Register....................................... 722
Offset 12h: TTMR - TCO Timer Initial Value Register ............................ 723
18.3 TCO Signal Usage............................................................................................ 723
18.3.1 INTRUDER# Signal ................................................................................. 723
18.3.2 Pin Straps ............................................................................................. 723
18.3.3 SMLINK Signals ..................................................................................... 723
18.4 TCO Theory of Operation .................................................................................. 723
18.4.1 Overview .............................................................................................. 723
18.4.2 Detecting a DOA CPU or System............................................................... 724
18.4.3 Handling an Operating System Lockup ...................................................... 724
18.4.4 Handling a CPU or Other Hardware Lockup ................................................ 725
18.4.5 Handling an Intruder .............................................................................. 725
18.4.6 Handling a Potentially Failing Power Supply ............................................... 725
18.4.7 Handling an ECC Error or Other Memory Error............................................ 726
18.4.8 SMM to Operating System and Operating System to SMM Calls .................... 726
18.4.9 Detecting an Improper FWH Programming ................................................. 726
18.4.10 IRQ1 and IRQ12 for Legacy Elimination .................................................... 726
18.5 Event Reporting via SMLink/SMBus ................................................................... 727
18.5.1 Overview .............................................................................................. 727
18.5.1.1 TCO Compatible Mode ..................................................................... 727
18.5.2 Message Format..................................................................................... 731
18.5.3 Connecting an External LAN Controller ...................................................... 732
19.0 LPC Interface: Bus 0, Device 31, Function 0........................................................... 733
19.1 Overview ....................................................................................................... 733
19.2 LPC Interface Configuration Register Details........................................................ 733
19.2.1 PCI Configuration Registers ..................................................................... 734
19.2.1.1
19.2.1.2
19.2.1.3
19.2.1.4
19.2.1.5
19.2.1.6
19.2.1.7
Offset 00h: ID: Vendor Identification Register .................................... 734
Offset 04h: CMD: Device Command Register ...................................... 735
Offset 06h: STS: Status Register ...................................................... 736
Offset 08h: RID - Revision ID Register............................................... 736
Offset 09h: CC: Class Code Register.................................................. 737
Offset 0Dh: MLT: Master Latency Timer Register ................................. 737
Offset 0Eh: HTYPE: Header Type Register .......................................... 738
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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