EP80579 Datasheet, PDF (585/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.4.1.71 Offset 134h: ERRSID - Error Source ID Register
This register reports the source (Requestor ID) of the first correctable and
uncorrectable (fatal or nonfatal) errors reported in the Root Error Status register. This
register is updated regardless of the settings of the Root Control register and the Root
Error Command register. These bits are sticky through reset.
Table 16-210.Offset 134h: ERRSID - Error Source ID Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 134h
Offset End: 137h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 134h
Offset End: 137h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 16
15 : 00
Bit Acronym
Bit Description
Sticky
UESID
CESID
Uncorrectable Error Source ID Requestor ID of the
source when an uncorrectable error (fatal or nonfatal) is
received, and the First Uncorrectable Error Detected bit is
not already set. Since this ID could be for an internally
detected error or from a message received from the other Y
end of the link, in the event of errors detected in the same
clock, priority is given to the error received from the link,
and that ID is what is logged. These bits are sticky through
system reset.
Correctable Error Source ID Requestor ID of the source
when an correctable error is received, and the First
Correctable Error Detected bit is not already set. Since this
ID could be for an internally detected error or from a
message received from the other end of the link, in the
Y
event of errors detected in the same clock, priority is given
to the error received from the link, and that ID is what is
logged. These bits are sticky through system reset.
Bit Reset
Value
0000h
0000h
Bit Access
RO
RO
16.4.1.72 Offset 140h: PEAUNITERR - PCI Express* Unit Error Register
This register is specific to the IMCH. It captures the non-PCI Express* unit errors
(those beyond the scope of the bus specification). The unit error mechanism is parallel
to that used by “compatible” error registers and masks, but cannot feed back into
standard registers because that would confuse standardized error handling software
(which would not understand the extracurricular error bits). Escalation is controlled via
the PEAERRDOCMD register (D2, F0:140-143h) for both standard and -specific error
types. Uncorrectable fatal errors feed into the fatal reporting select, Uncorrectable non-
fatal errors feed into the non-fatal reporting select, and correctable errors feed into the
correctable reporting select. The lower nibble is for HPC related errors.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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