EP80579 Datasheet, PDF (1545/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 37-145.INTBUS_ERR_STAT - Internal Bus Error Status Register (Sheet 2 of 2)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 0510h
Offset End: 0513h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 0510h
Offset End: 0513h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 0510h
Offset End: 0513h
Size: 32 bits
Default: 00000000h
Power
Well:
GbE0: Aux
Gbe1/2: Core
Bit Range
11 : 06
05 : 04
03 :02
01
Bit Acronym
Bit Description
Sticky
Rsvd
Type
Rsvd
MERR
Reserved
Internal Bus Error Type:
• 00 = Unsupported internal bus transaction targeted at
GbE
• 01 = Pull data error detected during a target write
transaction
• 10 = GbE received a Internal Bus Data Error response
while mastering a DMA transaction
• 11 = Master Pull data error occurred as a result of an
internal memory error
Reserved
Indicates whether one or more than one Internal Bus
errors have occurred before INTBUS_ERR_STAT.CERR was
cleared
0 = One Internal Bus Error
1 = More than one Internal Bus Error
Bit Reset
Value
0h
0h
0h
0h
Bit Access
RV
RO
RV
RWC
Internal Bus Error: Asserts when Internal Bus Error
status and address registers are valid
0 = no error has been logged
1 = Internal Bus Error status and address registers have
00
CERR
logged an error
If error handling is enabled (INTBUS_ERR_H_DIS = 0)
then this bit can only be cleared by a reset.
0h
RWC
37.6.8.2
MEM_TST – Memory Error Test Register
For software testability (in order to generate an ECC or parity error in hardware), this
register can be used to generate a hardware ECC or parity error in the GbE memories.
The selected ECC or parity error is continuously written in to the selected memory as
long as the memory is selected, at any address currently in use.
The ‘Select’ field allows selection of the memory that the errored data should be written
to. The ‘Mask’ field provides an XOR mask for the ECC or parity bits of that register.
Although a 16 bit mask is provided, not all registers use all bits of the Mask field. Refer
to the register description below.
The ECC or Parity error will not occur until the errored location has been read.
NOTE:
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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