EP80579 Datasheet, PDF (221/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 7-40. 0000h (IO) Base Address Registers in the IA F2 View
Offset Start Offset End
Register ID - Description
D0h
D1h
D0h
D1h
D4h
D5h
D6h
D7h
D8h
D9h
DAh
DBh
DCh
DDh
DEh
DFh
D0h
D1h
D0h
D1h
D4h
D5h
D6h
D7h
D8h
D9h
DAh
DBh
DCh
DDh
DEh
DFh
“Offset 08h: DMA_COMMAND - DMA Command Register” on page 770
“Offset 08h: DMA_COMMAND - DMA Command Register” on page 770
“Offset 08h: DMA_STATUS - DMA Status Register” on page 772
“Offset 08h: DMA_STATUS - DMA Status Register” on page 772
“Offset 0Ah: DMA_WSM - DMA Write Single Mask Register” on page 773
“Offset 0Ah: DMA_WSM - DMA Write Single Mask Register” on page 773
“Offset 0Bh: DMA_CHM - DMA Channel Mode Register” on page 774
“Offset 0Bh: DMA_CHM - DMA Channel Mode Register” on page 774
“Offset 0Ch: DMA_CBP - DMA Clear Byte Pointer Register” on page 775
“Offset 0Ch: DMA_CBP - DMA Clear Byte Pointer Register” on page 775
“Offset 0Dh: DMA_MC - DMA Master Clear Register” on page 775
“Offset 0Dh: DMA_MC - DMA Master Clear Register” on page 775
“Offset 0Eh: DMA_CM - DMA Clear Mask Register” on page 776
“Offset 0Eh: DMA_CM - DMA Clear Mask Register” on page 776
“Offset 0Fh: DMA_WAM - DMA Write All Mask Register” on page 777
“Offset 0Fh: DMA_WAM - DMA Write All Mask Register” on page 777
Default
Value
000X0X00b
000X0X00b
XXXXXXXh
XXXXXXXh
000001xxb
000001xxb
000000XXh
000000XXh
XXXXXXXXh
XXXXXXXXh
XXXXXXXXh
XXXXXXXXh
XXXXXXXXh
XXXXXXXXh
00001111b
00001111b
7.3.18
8254 Timers
The 8254 timers include the registers listed in Table 7-41. These registers materialize
at fixed locations in I/O space. See Chapter 31.0, “8254 Timers” for detailed discussion
of these registers.
Table 7-41. Summary of 8254 Timer Registers Mapped in I/O Space
Offset Start Offset End
Register ID - Description
Default
Value
43h
40h at 01h
40h at 01h
43h
40h at 01h
40h at 01h
“Offset 43h: TCW - Timer Control Word Register” on page 1146
XXh
“Offset 40h: TSB[0-2] - Interval Timer Status Byte Format Register” on page 1147 0XXXXXXXb
“Offset 40h: TCAP[0-2] - Interval Timer Counter Access Ports Register” on
page 1148
XXh
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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