EP80579 Datasheet, PDF (1437/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Note:
There are no special software timing requirements on accesses to IOADDR or IODATA.
All accesses will be immediate except when data is not readily available or acceptable.
In this case, the MAC will delay the results through normal bus methods.
Note:
Because a register/memory read or write takes two I/O cycles to complete, software
must provide a guarantee that the two I/O cycles occur as an atomic operation.
Otherwise, results can be non-deterministic from the software viewpoint.
37.6.1.2.3 Undefined I/O offsets
I/O offsets 0x08 through 0x3F are considered to reserved offsets with the I/O window.
Writes within this address region may cause unpredictable behavior. Reads within this
address region may return indeterminate values.
37.6.1.3
Register Conventions
All registers in the GbE are defined to be 32 bits and must be accessed with a DWORD
transaction.
• Reserved bit positions — Some registers contain certain bits that are marked as
“reserved”. These bits should never be written with anything other than their initial
value by software (indicated in their individual descriptions). Reads from registers
containing reserved bits may return indeterminate values in the reserved bit-
positions unless read values are explicitly stated. When read, these reserved bits
should be ignored by software.
• Reserved and/or undefined addresses — Any register address not explicitly
declared in this specification should be considered to be reserved, and should not
be written. Writing to reserved or undefined register addresses may cause
indeterminate behavior. Reads from reserved or undefined configuration register
addresses may return indeterminate values unless read values are explicitly stated
for specific addresses.
• Initial values — Most registers define the initial hardware values prior to being
programmed. In some cases, hardware initial values are undefined and will be
listed as such via the text “undefined”, “unknown”, or “X”. Some such configuration
values may need to be set by software in order for proper operation to occur; this
need is dependent on the function of the bit. Other registers may cite a hardware
default which is overridden by a higher-precedence operation. Operations which
may supersede hardware defaults may include completion of a hardware operation
(such as hardware auto-negotiation), or writing of a different register whose value
is then reflected in another bit.
For all registers, partial reads and writes may cause indeterminate behavior.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1437