EP80579 Datasheet, PDF (584/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-209.Offset 130h: RPERRMSTS - Root (Port) Error Message Status Register (Sheet
2 of 2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 130h
Offset End: 133h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 130h
Offset End: 133h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
03
02
01
00
Bit Acronym
Bit Description
Sticky
Multiple Uncorrectable Error Messages Detected In
the unlikely event of two first errors occurring during the
same clock period, only the first uncorrectable error
message bit is set. It takes an error to occur in a
subsequent clock to set this bit. These bits are sticky
through system reset.
MUEMD _{0 = Software clears this bit by writing a ‘1’ to the bit}
Y
location.
1 = Set when either a fatal or nonfatal error is received,
and the First Uncorrectable Error Detected bit is
already set. This indicates that one or more message
Requestor IDs were lost.
FUEMD
First Uncorrectable Error Message Detected The Root
Error Status bit reports status of error messages
(ERR_NONFATAL and ERR_FATAL) received by the root
complex, and of errors detected/reported (not masked) by
the Root Port itself. These bits are sticky through system
Y
reset.
0 = Software clears this bit by writing a ‘1’ to the bit
location.
1 = Set when the first fatal or nonfatal error is received.
Multiple Correctable Error Messages DetectedIn the
unlikely event of two first errors occurring during the same
clock period, only the first correctable error message bit is
set. It takes an error to occur in a subsequent clock to set
this bit. These bits are sticky through system reset.
MCEMD ^{0 = Software clears this bit by writing a ‘1’ to the bit}
Y
location.
1 = Set when a correctable error is received, and the First
Correctable Error Detected bit is already set. This
indicates that one or more message Requestor IDs
were lost.
First Correctable Error Message DetectedThe Root
Error Status bit reports status of error messages
(ERR_COR) received by the root complex, and of errors
detected/reported (not masked) by the Root Port itself.
FCEMD
These bits are sticky through system reset.
Y
0 = Software clears this bit by writing a ‘1’ to the bit
location.
1 = Set when the first correctable error is received.
Bit Reset
Value
0b
0b
0b
0b
Bit Access
RWC
RWC
RWC
RWC
Intel^® EP80579 Integrated Processor Product Line Datasheet
584
August 2009
Order Number: 320066-003US