EP80579 Datasheet, PDF (64/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
16-233 Offset 94h: RCVENAC - Receiver Enable Algorithm Control Register ......................... 611
16-234 Offset 98h: DSRETC - DRAM Self-Refresh (SR) Extended Timing and Control Register 611
16-235 Offset 9Ch: DQSFAIL1 - DQS Failure Configuration Register 1................................. 612
16-236 Offset A0h: DQSFAIL0 - DQS Failure Configuration Register 0................................. 613
16-237 Offset A4h: DRRTC00 - Receive Enable Reference Output Timing Control Register ..... 615
16-238 Offset A8h: DRRTC01 - Receive Enable Reference Output Timing Control Register ..... 616
16-239 Offset C4h: DRRTC02 - Receive Enable Reference Output Timing Control Register ..... 616
16-240 Offset B4h: DQSOFCS00 - DQS Calibration Register .............................................. 617
16-241 Offset B8h: DQSOFCS01 - DQS Calibration Register .............................................. 617
16-242 Offset C6h: DQSOFCS02 - DQS Calibration Register .............................................. 618
16-243 Offset BCh: DQSOFCS10 - DQS Calibration Register .............................................. 618
16-244 Offset C0h: DQSOFCS11 - DQS Calibration Register .............................................. 619
16-245 Offset C7h: DQSOFCS12 - DQS Calibration Register .............................................. 619
16-246 Offset CCh: WPTRTC0 - Write Pointer Timing Control Register................................. 620
16-247 Offset D0h: WPTRTC1 - Write Pointer Timing Control 1 Register .............................. 621
16-248 Offset D4h: DDQSCVDP0 - DQS Delay Calibration Victim Pattern 0 Register.............. 621
16-249 Offset D8h: DDQSCVDP1 - DQS Delay Calibration Victim Pattern 1 Register.............. 622
16-250 Offset DCh: DDQSCADP0 - DQS Delay Calibration Aggressor Pattern 0 Register ........ 622
16-251 Offset E0h: DDQSCADP1 - DQS Delay Calibration Aggressor Pattern 1 Register......... 623
16-252 Offset F0h: DIOMON - DDR I/O Monitor Register .................................................. 623
16-253 Offset F8h: DRAMISCTL - Miscellaneous DRAM DDR Cluster Control Register ............ 624
16-254 Offset C8h: DRAMDLLC - DDR I/O DLL Control Register ......................................... 625
16-255 Offset E8h: FIVESREG - Fixed 5s Pattern Register ................................................. 625
16-256 Offset ECh: AAAAREG - Fixed A Pattern Register ................................................... 626
16-257 Offset 140h: MBCSR - MemBIST Control Register ................................................ 626
16-258 Offset 144h: MBADDR - Memory Test Address Register.......................................... 629
16-259 Offset 148h: MBDATA[0:9] - Memory Test Data Register ....................................... 629
16-260 MBDATA Failure Address Register Correspondence to DRAM Address ....................... 631
16-261 BL4 Column and Chunk Correspondence to DRAM Address ..................................... 631
16-262 BL8 Column and Chunk Correspondence to DRAM Address ..................................... 631
16-263 Offset 19Ch: MB_START_ADDR - Memory Test Start Address Register .................... 632
16-264 Offset 1A0h: MB_END_ADDR - Memory Test End Address Register .......................... 632
16-265 Offset 1A4h: MBLFSRSED - Memory Test Circular Shift and LFSR Seed Register ........ 633
16-266 Offset 1A8h: MBFADDRPTR - Memory Test Failure Address Pointer Register .............. 633
16-267 Offset 1B0h: MB_ERR_DATA00 - Memory Test Error Data 0 ................................... 634
16-268 Offset 1B4h: MB_ERR_DATA01 - Memory Test Error Data 0 ................................... 634
16-269 Offset 1B8h: MB_ERR_DATA02 - Memory Test Error Data 0 ................................... 634
16-270 Offset 1BCh: MB_ERR_DATA03 - Memory Test Error Data 0 ................................... 635
16-271 Offset 1C0h: MB_ERR_DATA04 - Memory Test Error Data 0 ................................... 635
16-272 Offset 1C4h: MB_ERR_DATA10 - Memory Test Error Data 1 ................................... 635
16-273 Offset 1C8h: MB_ERR_DATA11 - Memory Test Error Data 1 ................................... 636
16-274 Offset 1CCh: MB_ERR_DATA12 - Memory Test Error Data 1 .................................. 636
16-275 Offset 1D0h: MB_ERR_DATA13 - Memory Test Error Data 1 .................................. 636
16-276 Offset 1D4h: MB_ERR_DATA14 - Memory Test Error Data 1 .................................. 637
16-277 Offset 1D8h: MB_ERR_DATA20 - Memory Test Error Data 2 .................................. 637
16-278 Offset 1DCh: MB_ERR_DATA21 - Memory Test Error Data 2 .................................. 637
16-279 Offset 1E0h: MB_ERR_DATA22 - Memory Test Error Data 2 ................................... 638
16-280 Offset 1E4h: MB_ERR_DATA23 - Memory Test Error Data 2 ................................... 638
16-281 Offset 1E8h: MB_ERR_DATA24 - Memory Test Error Data 2 ................................... 638
16-282 Offset 1ECh: MB_ERR_DATA30 - Memory Test Error Data 3 ................................... 639
16-283 Offset 1F0h: MB_ERR_DATA31 - Memory Test Error Data 3 ................................... 639
16-284 Offset 1F4h: MB_ERR_DATA32 - Memory Test Error Data 3 ................................... 639
16-285 Offset 1F8h: MB_ERR_DATA33 - Memory Test Error Data 3 ................................... 640
16-286 Offset 1FCh: MB_ERR_DATA34 - Memory Test Error Data 3 ................................... 640
16-287 Offset 260h: DDRIOMC0 - DDRIO Mode Register Control Register .......................... 641
Intel^® EP80579 Integrated Processor Product Line Datasheet
64
August 2009
Order Number: 320066-003US