EP80579 Datasheet, PDF (1216/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 34-1. Bus 0, Device 4, Function 0: Summary of PCI-to-PCI Bridge PCI Configuration
Registers (Sheet 2 of 2)
Offset Start Offset End
Register ID - Description
Default
Value
28h
2Ch
30h
32h
34h
3Ch
3Dh
3Eh
DCh
DDh
DEh
E0h
E2h
28h
2Ch
31h
33h
34h
3Ch
3Dh
3Fh
DCh
DDh
DFh
E1h
E2h
“Offset 28h: PMBASU: Memory Limit Register” on page 1226
“Offset 2Ch: PMLMTU: Prefetchable Memory Limit Upper Register” on page 1226
“Offset 30h: IOBU: I/O Base Upper Register” on page 1227
“Offset 32h: IOLU: I/O Limit Upper Register” on page 1227
“Offset 34h: CP: Capabilities Pointer Register” on page 1227
“Offset 3Ch: IRQL: Interrupt Line Register” on page 1228
“Offset 3Dh: IRQP: Interrupt Pin Register” on page 1228
“Offset 3Eh: BCTL: Bridge Control Register” on page 1228
“Offset DCh: PCID: Power Management Capability ID Register” on page 1229
“Offset DDh: PCP: Power Management Next Capability Pointer Register” on
page 1230
“Offset DEh: PMCAP: Power Management Capability Register” on page 1230
“Offset E0h: PMCS: Power Management Control and Status Register” on
page 1231
“Offset E2h: PMCSE: Power Management Control and Status Extension Register”
on page 1232
Fh
0
0
0
dch
0
0
0000h
01h
00h
0023h
0008h
0000h
34.2.1
PCI-to-PCI Bridge Header
The PCI-to-PCI bridge header format is given in Table 34-2.
Table 34-2. PCI-to-PCI Bridge PCI Header
Byte Offset
+7
+6
+5
+4
Status
Command
BIST
Type
LT
CLS
Base Address 1
Secondary Status
I/O Limit
I/O Base
Pref. Mem. Limit
Pref. Mem. Base
Prefetchable Limit Upper 32 bits
Reserved
CP
Bridge Control
IRQ P
IRQ L
+3
+2
+1
+0
Device ID
Vendor ID
Class Code
Rev
Base Address 0
Scdry. Lat.
Timer
Subord.
Bus Num
Scdry. Bus
Num
Primary
Bus Num
Memory Limit
Memory Base
Prefetchable Base Upper 32 bits
I/O Limit Upper
I/O Base Upper
Expansion ROM Base
Intel^® EP80579 Integrated Processor Product Line Datasheet
1216
August 2009
Order Number: 320066-003US