EP80579 Datasheet, PDF (392/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.1.1.3
Offset 04h: PCICMD: PCI Command Register
Since IMCH Device 0 does not physically reside on a PCI bus, many of the bits are not
supported.
Table 16-4. Offset 04h: PCICMD: PCI Command Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 04h
Offset End: 05h
Size: 16 bit
Default: 0006h
Power Well: Core
Bit Range
15 : 10
09
08
07
06
05 : 03
02
01
00
Bit Acronym
Bit Description
Sticky
Reserved
FB2B
SERRE
Reserved
PERRE
Reserved
BME
MAE
Reserved
Reserved
Fast Back-to-Back Enable: This bit is hardwired to 0.
SERR Enable: This bit is a global enable bit for Device 0
SERR messaging. The IMCH does not have a SERR signal.
The IMCH communicates the SERR condition by sending a
SERR message over NSI to the IICH.
0 = Disable. The SERR message is not generated by the
IMCH for Device 0.
1 = Enable. The IMCH enables generation of SERR
messages over NSI for specific Device 0, Function 0
error conditions that are enabled via the PCICMD
register. The error status is reported in the PCISTS
registers. The only error event enabled through
Device 0, Function 0 is Detected Parity Error which is
essentially a NSI poisoned TLP, and is enabled by the
parity error enable bit (PERRE).
Note: This bit only controls SERR messaging for Device
0, Function 0. Device 0, Function 1, and Devices
1-7 have their own SERR bits to control error
reporting for error conditions occurring on their
respective devices. The control bits are used in a
logical OR manner to enable the SERR NSI
message mechanism.
Reserved
Parity Error Enable:
0 = Disable. The IMCH does not take any action when it
detects data corruption on NSI.
1 = Enable. The IMCH generates an SERR message over
the NSI to the IICH when a poisoned TLP is detected
by the IMCH on NSI (DPE set in PCISTS) and SERRE is
set to 1.
Reserved
Bus Master Enable: The IMCH is always enabled as a
master on NSI. This bit is hardwired to 1. Writes to this bit
position have no effect.
Memory Access Enable: This bit is hardwired to 1.
Reserved
Bit Reset
Value
00h
0b
0b
0b
0b
0h
1b
1b
0b
Bit Access
RO
RW
RW
RO
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
392
August 2009
Order Number: 320066-003US