EP80579 Datasheet, PDF (1552/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.7.4.1 Power up (off to Dr to D0u to D0a)
Figure 37-51.Reset Deasserted after 1st EEPROM Read Completes
power
tppg
1
PWR_OK
CLK
trpg
RESET
Reading EEPROM
tpgee
2
tee
Read EEPROM
5
tpgprst
6
tclkpr
7
tpree
tee
Read EEPROM
tprmem 10 _{Memory Access Enable 11}
Wakeup Enabled
DState
4
APM
Dr
4
APM
D0u
D0a
Note
1
2
4
5
7
10
11
PWR_OK must not be asserted until all power supplies are good
An EEPROM read is started on the rising edge of PWR_OK and RESET.
APM Wakeup may be enabled based on what is read from the EEPROM.
The system can delay an arbitrary time before deasserting RESET.
The deassertion edge of RESET will cause the EEPROM to be re-read and Wake Up disabled.
The system can delay an arbitrary time before enabling Memory Access.
Writing a 1 to the Memory Access Enable bit in the PCI Command Register will transition the
MAC from D0u to D0 state
Intel^® EP80579 Integrated Processor Product Line Datasheet
1552
August 2009
Order Number: 320066-003US