EP80579 Datasheet, PDF (577/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-201.Offset 110h: CORERRSTS - Correctable Error Status Register (Sheet 2 of 2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 110h
Offset End: 113h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 110h
Offset End: 113h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
07
06
05 : 01
00
Bit Acronym
Bit Description
Sticky
BDS
Bad DLLP Status: This bit is set when the calculated DLLP
CRC is not equal to the received value. This bit is sticky
through system reset.
Y
0 = Cleared by writing a ‘1’ to the bit location.
1 = Bad DLLP detected.
Bad TLP Status:
0 = TLP status good.
BTS
1 = This bit is set when the calculated TLP CRC is not
Y
equal to the received value. Also included are invalid
sequence numbers.
Reserved Reserved
RES
Receiver Error Status: Optional PCI Express*
specification bit, implemented for IMCH.
Data is delivered over PCI Express* via packets built out of
8b/10b symbols. Receiver Error Status register is set for
8b/10b errors received, framing errors received
Y
irrespective of the packet boundaries.
0 = Cleared by writing a ‘1’ to the bit location.
1 = Receiver Error detected.
Bit Reset
Value
0b
0b
000b
0b
Bit Access
RWC
RWC
RWC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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