EP80579 Datasheet, PDF (876/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.5.2
23.5.2.1
Error Handling
Errors on DMI
Errors on the memory interface will cause the following behavior:
Cycle Type
I/O, Config Write
I/O, Config Read
Memory Write (to HC)
Memory Read (to HC)
Memory Write
(from HC)
Memory Read
(from HC)
I/O, Cfg Completion
(read and write)
Mem. Read Comp.
(from HC)
Mem. Read Comp. (to HC)
Address/Cmd Parity Error
Data Parity Error
Set DPE bit
Do not claim cycle
Set DPE bit
Do not claim cycle
Not supported
NA
Set DPE bit
Claim Cycle, data dropped
Return completion success
NA
NA
NA
NA
NA
TAbort
MAbort
NA
NA
NA
NA
NA
NA
NA
NA
NA
MAI Not Supp
NA
NA
NA
MAI Not Supp
NA
NA
NA
NA
NA
NA
• Set DPE,
• Do not claim cycle
• Set Error bit in bus
master I/O space, offset
02h, bit 1
• Stop DMA engine
Needs a system reset to
recover
Set DPE & DPD, Claim cycle
• During PRD data transfer,
abort DMA operation and set
Error bit in bus master I/O
space;
• During DMA data transfer,
propagate the error to the
device through crc error
without setting Error Status
bit.
Set RTA bit.
Set Error bit
and abort
MAI
Not Supp
MAI
Not Supp
Set RMA bit.
Set Error bit
and abort
23.5.2.2
Errors on SATA Interface
There are several errors that can occur on the SATA interface which may interrupt a
data transfer.
There are two aspects from the following tables that are important when.
• Errors that occur during DMA data in transfers (device sending data) that will result
in data corruption will set the bus master error status bit (bit 1 of I/O offset 01h for
primary, bit 1 of I/O offset 05h for secondary), while it may or may not set the bit
during other cases. If the SATA device generates R_ERR on DMA data out transfers
(host sending data), the bus master error status bit will be set, while it may or may
not be set on other transfers.
• Errors that occur in PIO or DMA data in transfers (device generating data) that will
result in data corruption will cause the SATA host controller to generate R_ERR on
the SATA interface.
If the bus master error bit does get set for PIO transfers or non-data portions, it is
acceptable.
Table 1448 breaks out conditions for the above rules. Additionally, other errors that
may occur are listed for information purposes.
Intel^® EP80579 Integrated Processor Product Line Datasheet
876
August 2009
Order Number: 320066-003US