EP80579 Datasheet, PDF (1368/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Note:
Descriptors with the null address (0), or zero length, transfer no data. If they have the
RS bit in the command byte set, then the DD field in the status word is written after
hardware processes them. Hardware only sets the DD bit for descriptors with RS set.
Note:
Null Descriptors are intended for padding descriptor queues, in case a specific
alignment of descriptors comprising a packet are desired. Null transmit descriptors
should not be used to convey any meaningful command information (such as EOP);
they are consumed with no processing other than status reporting (if requested).
Note:
Hardware is considered “done processing” a descriptor when any data specified in the
descriptor has been completely fetched and loaded in the transmit FIFO.
Note:
VLE, IFCS, and IC are qualified by EOP. In other words, hardware interprets these bits
ONLY when EOP is set.
IDE activates a transmit interrupt delay timer. Hardware loads a countdown register
when it writes back a transmit descriptor that has RS and IDE set. The value loaded
comes from Transmit Interrupt Delay Value Register (TIDV.IDV). When the count
reaches 0, a transmit interrupt occurs if transmit descriptor write-back interrupts
(ICR.TXDW) are enabled. Hardware always loads the transmit interrupt counter
whenever it processes a descriptor with IDE set even if it is already counting down due
to a previous descriptor. If hardware encounters a descriptor that has RS set, but not
IDE, it generates an interrupt immediately after writing back the descriptor and the
interrupt delay timer is cleared.
Note:
Although the transmit interrupt may be delayed, the descriptor write-back requested
by setting the RS bit is performed without delay unless descriptor write-back bursting is
enabled. See Section 37.6.5.10, “TXDCTL – Transmit Descriptor Control Register”.
VLE indicates that the packet is a VLAN or ISL packet (i.e. that the hardware should
add the VLAN Ethertype and an 802.1q VLAN tag to the packet).
Note:
If the VLE bit is set, the CTRL.VME bit should also be set to enable VLAN tag insertion.
If the CTRL.VME bit is not set, the device will not insert VLAN tags on outgoing packets,
but may instead insert ISL headers.
Table 37-2. VLAN Tag Insertion Decision Table when VLAN Mode Enabled (CTRL.VME=1)
VLE
0
1
Action
Send generic Ethernet packet. IFCS controls insertion of FCS in normal Ethernet
packets.
Send 802.1Q packet; the Ethernet Type field comes from the VET register and the
VLAN data comes from the special field of the TX descriptor; hardware always
appends the FCS/CRC.
Three bits provide transmit status. These are only present in cases where RS is set in
the command. DD indicates that the descriptor is done and is written back after the
descriptor has been processed. The bits EC and LC indicate collision behavior when in
half-duplex mode. They have no meaning when in full-duplex mode.
Figure 37-19.Transmit Status Layout (TDESC.STATUS)
3
2
1
0
TU
LC
EC
DD
TU: Transmit Underrun
LC: Late Collision
EC: Excess Collisions
Intel^® EP80579 Integrated Processor Product Line Datasheet
1368
August 2009
Order Number: 320066-003US