EP80579 Datasheet, PDF (858/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.3.3
23.3.3.1
Port DMA Registers
Offset 100h: PxCLB[0-1] – Port [0-1] Command List Base Address
Register
Table 23-56. Offset 100h: PxCLB[0-1] – Port [0-1] Command List Base Address Register
Description:
View: PCI
BAR: ABAR
Bus:Device:Function: 0:31:2
Offset Start: 100h, 180h
Offset End: 17Fh, 1FFh
Size: 32 bit
Default: Variable
Power Well: Core
Bit Range
31 : 10
09 : 00
Bit Acronym
Bit Description
Sticky
CLB
Reserved
Command List Base Address (CLB): Indicates the 32-
bit base for the command list for this port. This base is
used when fetching commands to execute. This address
must be 1K aligned as indicated by bits 31:10 being read/
write.
Note that these bits are not reset on a HBA reset.
Reserved
Bit Reset
Value
Variable
000h
Bit Access
RW
RO
23.3.3.2 Offset 104h: PxCLBU[0-1] – Port [0-1] Command List Base Address
Upper 32-bits Register
Table 23-57. Offset 104h: PxCLBU[0-1] – Port [0-1] Command List Base Address Register
Description:
View: PCI
BAR: ABAR
Bus:Device:Function: 0:31:2
Offset Start: 104h, 184h
Offset End: 107h, 187h
Size: 32 bit
Default: Variable
Power Well: Core
Bit Range
31 : 00
Bit Acronym
Bit Description
Sticky
CLBU
Command List Base Address Upper (CLBU): Indicates
the upper 32-bits for the command list base address for
this port. This base is used when fetching commands to
execute.
Note that these bits are not reset on a HBA reset.
Bit Reset
Value
Variable
Bit Access
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
858
August 2009
Order Number: 320066-003US