EP80579 Datasheet, PDF (565/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-190.Offset 76h: PEALNKSTS - PCI Express Link Status Register (Sheet 2 of 2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 76h
Offset End: 77h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 76h
Offset End: 77h
Size: 16 bit
Default: 1001h
Power Well: Core
Bit Range
10
09 : 04
03 : 00
Bit Acronym
Bit Description
Sticky
Reserved
NW
LS
Reserved:
Negotiated Width: Note that reset value is reserved, and
this field remains undefined until bit 11 (Link Training) has
been cleared by hardware. If training never completes, this
field remains undefined.
000001b = x1
000100b = x4
001000b = x8
All other encodings are reserved
Link Speed: Value of 1h indicates 2.5 GBytes/s link.
Bit Reset
Value
0b
00h
1h
Bit Access
RO
RO
RO
16.4.1.52 Offset 78h: PEASLTCAP - PCI Express* Slot Capabilities Register
This register identifies PCI Express* slot specific capabilities. Hot Plug is not supported.
Table 16-191.Offset 78h: PEASLTCAP - PCI Express Slot Capabilities Register (Sheet 1 of
2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 78h
Offset End: 7Bh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 19
18 : 17
16 : 15
14 : 07
Bit Acronym
Bit Description
Sticky
PSN
Reserved
SPLS
SPLV
Physical Slot Number: This hardware initialized field
indicates the physical slot number attached to this port.
This field must be hardware initialized to a value that
assigns a slot number that is globally unique within the
chassis. This field must be initialized to 0 for ports
connected to devices that are either integrated on the
motherboard.
Reserved
Slot Power Limit Scale: Specifies the scale used for the
Slot Power Limit Value.
00b = 1.0X (25.5–255)
01b = 0.1X (2.55–25.5)
10b = 0.01X (0.255–2.55)
11b = 0.001X (0.0–0.255)
Slot Power Limit Value: In combination with the Slot
Power Limit Scale value, this register specifies the upper
limit on power supplied by slot. Power limit (in watts)
calculated by multiplying the value in this field by the value
in the Slot Power Limit Scale field. This field must be
programmed at boot. Writing to this field triggers a
Set_Slot_Power_Limit inband PCI Express* message.
Bit Reset
Value
000h
00b
00b
00h
Bit Access
RWO
RWO
RWO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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