EP80579 Datasheet, PDF (151/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 5-15. Summary of LPC Interface Error Reporting Capabilities
Feature
Implementation
Logging Details The LPC interface captures the type of event detected in the STS register.
Reporting Multiple
Errors
The LPC interface does not capture multiple events.
Data Poisoning IICH backbone does not support data poisoning.
For additional details on error handling in the LPC interface, see Section 19.0, “LPC
Interface: Bus 0, Device 31, Function 0”.
5.4.3
USB 1.1 Interface
The IICH provides a USB 1.1 controller that can generate an interrupt on error events
and can also use the PCI SERR infrastructure to report errors. Table 5-16 summarizes
the error conditions that the controller reports.
.
Table 5-16. Summary of USB 1.1 Interface Error Conditions
Event
Type
Fatality^a
Reports via
Notes
Host Controller
Process Error
Uncorrectable
Host System Error Uncorrectable
USB Error
Uncorrectable
Parity Error
Uncorrectable
Fatal
Fatal
Fatal
Fatal
Interrupt
Interrupt
Interrupt
SERR
Consistency check by host controller
fails while processing a TD.
Serious error during host system
access involving HC module.
USB transaction completion ended in
error.
Parity error on read completion
returned to host controller or UHCI
register write.
a. “Fatal” events result in data loss or data corruption that the unit cannot repair, “Non-Fatal” events do not.
Table 5-17 summarizes the capabilities of the USB 1.1 controller error handling for each
of the features that the unit is expected to provide.
Table 5-17. Summary of USB 1.1 Interface Error Reporting Capabilities
Feature
Implementation
Enabling and
Masking Error
Reporting
The CMD and USBINTR registers supports error enabling and masking.
Logging Details
The USB 1.1 interface captures the type of event detected in the DSR and USBSTS
registers.
Reporting Multiple The USB 1.1 interface does not capture multiple events, error events cause the interface
Errors
to halt operation until serviced by software.
Data Poisoning IICH backbone does not support data poisoning.
For additional details on error handling in the USB 1.1 controller, see Section 25.0,
“USB (1.1) Controller: Bus 0, Device 29, Function 0”.
5.4.4
USB 2.0 Interface
The IICH provides a USB 2.0 controller that can generate an interrupt on error events
and can also use the PCI SERR infrastructure to report errors. Table 5-18 summarizes
the error conditions that the controller reports.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
151