EP80579 Datasheet, PDF (1443/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 37-27. CTRL_EXT: Extended Device Control Register (Sheet 2 of 2)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 0018h
Offset End: 001Bh
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 0018h
Offset End: 001Bh
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 0018h
Offset End: 001Bh
Size: 32 bit
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range
15
14
13
12
11 : 00
Bit Acronym
Bit Description
Sticky
SPD_BYPS
Rsvd
EE_RST
Rsvd
Rsvd
Speed Select Bypass.
0 = Normal speed detection mechanisms are used to
determine the speed of the MAC.
1 = All speed detection mechanisms are bypassed and the
MAC is immediately set to the setting of CTRL.SPEED.
Note: CTRL_EXT.SPD_BYPS performs a function similar
to CTRL.FRCSPD in that the device's speed
settings are determined by the value software
writes to the CTRL.SPEED bits. However, when
using CTRL_EXT.SPD_BYPS the CTRL.SPEED
setting takes effect immediately, when using
CTRL.FRCSPD the CTRL.SPEED setting waits until
after the device's clock switching circuitry
performs the change.
Reserved
EEPROM Reset
Initiates a “reset-like” event to the EEPROM function. This
causes the EEPROM to be read as if a UNIT_RESET had
occurred. All device functions should be disabled prior to
setting this bit. This bit is self-clearing.
NOTE: this will not cause the controller to detect the
EEPROM
Reserved
Reserved
Bit Reset
Value
0h
0h
0h
0h
0h
Bit Access
RW
RV
RW
RV
RV
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1443