EP80579 Datasheet, PDF (1475/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 37-50. RCTL: Receive Control Register (Sheet 2 of 4)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 0100h
Offset End: 0103h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 0100h
Offset End: 0103h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 0100h
Offset End: 0103h
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range
22
21
20
19
18
Bit Acronym
Bit Description
Sticky
DPF
Rsvd
CFI
CFIEN
VFE
Discard Pause Frames. This bit controls the DMA
function of flow control packets addressed to the station
address (RAH/RAL[0]). If a packet is a valid flow control
packet and is addressed to the station address it will not be
DMA'd to host memory if RCTL.DPF=1.
0 = Incoming frames are subject to filter comparison
1 = Incoming valid PAUSE frames discarded even if they
match any of the filter registers
Reserved
Canonical Form Indicator. One of the three bits that control
the VLAN filter table. This bit may be compared to the CFI
bit found in the 802.1q packet as part of the acceptance
criteria. RCTL.CFIEN and RCTL.VFE determine whether or
not this comparison takes place.
Canonical Form Indicator Enable. One of the three bits
that control the VLAN filter table. This bit enables using the
CFI bit found in the 802.1q packet as part of the
acceptance criteria.
The next two are used to decide whether the CFI bit found
in the.1Q packet should be used as part of the acceptance
criteria.
0 = CFI Disabled: bit not compared to determine packet
acceptance
1 = CFI from packet must match CFI field for acceptance
of 802.1q packet
VLAN Filter Enable. One of the three bits that control the
VLAN filter table. This bit determines whether the table
participates in the packet acceptance criteria.
0 = Disabled, filter table does not decide packet
acceptance
1 = Enabled, filter table decides acceptance of 802.1q
packets
Bit Reset
Value
0h
0h
0h
0h
0h
Bit Access
RW
RV
RW
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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