EP80579 Datasheet, PDF (806/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 22-2. GPIO Summary Table (Sheet 2 of 2)
GPIO# PowerWell Muxed
27:28
29
30:31
32
33:34
35:39
40
41
42:47
48
49
50:63
Resume
Yes
Core
Yes
Core
Yes
Unimplemented
Core
Yes
Unimplemented
Core
Yes
Core
Yes
Unimplemented
Core
No
Unimplemented
Unimplemented
GPIO_USE_SEL
1 when GPIO,
0 when IRQ
RW – D = 0
1 when GPIO,
0 when IRQ
Always 0
1 when GPIO,
0 when IRQ
Always 0
1 when GPIO,
0 when IRQ
RW – D = 0
Always 0
Always 1
Always 0
Always 0
GP_IO_SEL
1 when IRQ,
0/1 when GPIO
Always 1
Always 1
Reserved 0
1 when IRQ,
0/1 when GPIO
Always 0
Always 1
Always 1
Always 0
Always 0
Always 0
Always 0
GP_LVL
RW – D=1
Always 1
Always 1
Reserved 0
RW – D=1
Always 0
Always 0
Always 1
Always 0
RW – D=1
Always 0
Always 0
GPO_BLINK
RW – D=0
Always 0
Always 0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Notes:
1.
N/A - Not Applicable, since the relevant registers bit do not exist for these GPIO.
2.
Reserved - The bit access type may be RW but it is a reserved bit.
3.
RW – D=1: The bit access type is RW; default value is 1.
GPI_INV
Always 0
Always 0
Always 0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
22.2
Note:
General Purpose I/O-Mapped Configuration Register
Details
The control for the general purpose I/O signals is handled through separate 64-byte I/
O space. The General Purpose I/O configuration registers are mapped into I/O space
using register GBA in the PCI configuration space for device 31, function 0 (see Section
19.2.2.3, “Offset 48h: GBA: GPIO Base Address Register” on page 740).
For the following registers, if a bit is allocated for a GPIO that doesn’t exist, unless
otherwise indicated, the bit always reads 0 and values written to that bit have no
effect.
Table 22-3. Bus 0, Device 31, Function 0: Summary of General Purpose I/O Configuration
Registers Mapped Through GBA BAR IO BAR (Sheet 1 of 2)
Offset Start Offset End
Register ID - Description
Default
Value
00h
03h
“Offset 00h: GPIO_USE_SEL1 - GPIO Use Select 1 {31:0} Register” on page 807 Variable
04h
07h
“Offset 04h: GP_IO_SEL1 - GPIO Input/Output Select 1 {31:0} Register” on
page 808
E400FFFFh
0Ch
0Fh
“Offset 0Ch: GP_LVL1 - GPIO Level 1 for Input or Output {31:0} Register” on
page 809
FF3F0000h
18h
1Bh
“Offset 18h: GPO_BLINK - GPIO Blink Enable Register” on page 810
00040000h
2Ch
2Fh
“Offset 2Ch: GPI_INV - GPIO Signal Invert Register” on page 812
00000000h
Intel^® EP80579 Integrated Processor Product Line Datasheet
806
August 2009
Order Number: 320066-003US