EP80579 Datasheet, PDF (732/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 18-14. SMBus Message Format
Data Byte 7
Data Byte 8
Reserved
A
Reserved
AP
0000000010000000011
Table 18-15. Message Address Byte
Field
Start
Address
Dir
Ack
Bit Length
Comment
1
‘1’ to indicate the start of a packet
7
LAN SMBus Address. Is always 1100100.
1
‘0’ to indicate write cycle
1
Returned by External LAN Controller
Note:
For the System Power State field: 00 = G0, 01 = G1, 10 = G2, 11=PreBoot. The
preboot state is entered when the SLP_S3#, SLP_S4# and SLP_S5# signals go from
low to high. The indication switches to the G0 state when CPURESET Done ACK
completion packet sent to the IMCH. This corresponds to the time when the CPU has
been reset. If the CPU is locked up, then the CPU EVENT bit is set.
18.5.3
Connecting an External LAN Controller
The CMI’s TCO logic sends the message on the SMLINK signals in TCO compatible
mode. An External LAN Controller claims these cycles.
When sending the messages to the external LAN Controller, the CMI’s IICH abides by
the standard SMBus rules associated with collision detection. It delays starting a
message until the link is idle, and detects collisions. If a collision is detected, the CMI
drops that message.
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Intel^® EP80579 Integrated Processor Product Line Datasheet
732
August 2009
Order Number: 320066-003US