EP80579 Datasheet, PDF (960/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
25.2.1.5
FRBASEADD: Frame List Base Address Register
This 32-bit register contains the beginning address of the Frame List in the system
memory. HCD loads this register prior to starting the schedule execution by the Host
Controller. When written, only the upper 20 bits are used. The lower 12 bits are written
as zero (4 Kbyte alignment). The contents of this register are combined with the frame
number counter to enable the Host Controller to step through the Frame List in
sequence. The two least significant bits are always 00. This requires DWord alignment
for all list entries. This configuration supports 1024 Frame List entries.
Table 25-26. FRBASEADD: Frame List Base Address Register
Description:
View: PCI
BAR: USBIOBAR (IO)
Bus:Device:Function: 0:29:0
Offset Start: 08h
Offset End: 0Bh
Size: 32 bit
Default: XXXXX000h
Power Well: Core
Bit Range
31 : 12
11 : 00
Bit Acronym
Bit Description
BAD
Reserved
Base Address: These bits correspond to memory
address signals [31:12], respectively.
Reserved. Must be written as 0s.
Sticky
Bit Reset
Value
X
0h
Bit Access
RW
25.2.1.6
SOFMOD: Start of Frame Modify Register
This 1-byte register is used to modify the value used in the generation of SOF timing on
the USB. Only the 7 least significant bits are used. When a new value is written into the
these 7 bits, the SOF timing of the next frame will be adjusted. This feature can be
used to adjust out any offset from the clock source that generates the clock that drives
the SOF counter. This register can also be used to maintain real time synchronization
with the rest of the system so that all devices have the same sense of real time. Using
this register, the frame length can be adjusted across the full range required by the
USB Specification. Its initial programmed value is system dependent based on the
accuracy of hardware USB clock and is initialized by system BIOS. It may be
reprogrammed by USB system software at any time. Its value will take effect from the
beginning of the next frame. This register is reset upon a Host Controller Reset or
Global Reset. Software must maintain a copy of its value for reprogramming if
necessary.
Intel^® EP80579 Integrated Processor Product Line Datasheet
960
August 2009
Order Number: 320066-003US