EP80579 Datasheet, PDF (1585/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
39.6
Register Summary
The default value for all registers is 0h, unless otherwise noted. All registers starting at
20h are implemented in SRAM without guaranteed reset values. It is the responsibility
of either BIOS or SW to initialize these to 0.
For more information on the conventions the following register summaries adopt, see
Section 7.1, “Overview of Register Descriptions and Summaries” on page 183.
The CAN registers materialize in the PCIspace.
Table 39-4 and Table 39-5 summarize the CAN interface #0 and #1 materializations
from the PCI perspective.
Table 39-4. Bus M, Device 4, Function 0: Summary of CAN Registers Mapped Through
CSRBAR Memory BAR
Offset Start Offset End
Register ID - Description
Default
Value
00000000h 00000003h “Offset 00000000h: Int_Status - Interrupt Status Register” on page 1587
00000000h
00000004h 00000007h “Offset 00000004h: Int_Ebl - Interrupt Enable Register” on page 1588
00000000h
00000008h 0000000Ah “Offset 00000008h: Buffer Status Indicators” on page 1589
00000000h
0000000Ch 0000000Fh “Offset 0000000Ch: ErrorStatus - Error Status Indicators” on page 1590
00000000h
00000010h 00000013h “Offset 00000010h: Command - Operating Modes” on page 1591
00000000h
00000014h 00000017h “Offset 00000014h: Config - CAN Configuration Register” on page 1592
00000000h
00000020h at 00000023h at “Offset 00000020h: TxMessageControl[0-7] - Transmit Message Control and
10h
10h
Command” on page 1593
XXXXXXXXh
00000024h at
10h
00000027h at
10h
“Offset 00000024h: TxMessageID[0-7] - Transmit Message ID” on page 1595
XXXXXXXXh
00000028h at 0000002Ah at “Offset 00000028h: TxMessageDataHigh[0-7] - Transmit Message Data High” on
10h
10h
page 1596
XXXXXXXXh
0000002Ch at 0000002Fh at “Offset 0000002Ch: TxMessageDataLow[0-7] - Transmit Message Data Low” on
10h
10h
page 1597
XXXXXXXXh
000000A0h at 000000A3h at “Offset 000000A0h: RxMessageControl[0-15] - Receive Message Command and
20h
20h
Control” on page 1598
XXXXXXXXh
000000A4h at
20h
000000A7h at
20h
“Offset 000000A4h: RxMessageID[0-15] - Receive Message ID” on page 1600
XXXXXXXXh
000000A8h at 000000ABh at “Offset 000000A8h: RxMessageDataHigh[0-15] - Receive Message Data High” on
20h
20h
page 1600
XXXXXXXXh
000000ACh at 000000AFh at “Offset 000000ACh: RxMessageDataLow[0-15] - Receive Message Data Low” on
20h
20h
page 1601
XXXXXXXXh
000000B0h at
20h
000000B3h at
20h
“Offset 000000B0h: RxMessageAMR[0-15] - Receive Message AMR” on page 1601
XXXXXXXh
000000B4h at
20h
000000B7h at
20h
“Offset 000000B4h: RxMessageACR[0-15] - Receive Message ACR” on page 1602
XXXXXXXXh
000000B8h at
20h
000000BBh at
20h
“Offset 000000B8h: RxMessageAMR_Data[0-15] - Receive Message AMR Data” on
page 1603
XXXXXXXXh
000000BCh at
20h
000000BFh at
20h
“Offset 000000BCh: RxMessageACR_Data[0-15] - Receive Message ACR Data” on
page 1604
XXXXXXXXh
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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