EP80579 Datasheet, PDF (56/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
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Summary of IMCH EDMA Error Reporting Capabilities ............................................ 147
Summary of IMCH PCI-Express Error Conditions ................................................... 148
Summary of IMCH PCI-Express Error Reporting Capabilities.................................... 149
Summary of SMBus Interface Error Conditions...................................................... 150
Summary of SMBus Controller Error Reporting Capabilities ..................................... 150
Summary of LPC Interface Error Conditions .......................................................... 150
Summary of LPC Interface Error Reporting Capabilities .......................................... 150
Summary of USB 1.1 Interface Error Conditions.................................................... 151
Summary of USB 1.1 Interface Error Reporting Capabilities .................................... 151
Summary of USB 2.0 Interface Error Conditions.................................................... 152
Summary of USB 2.0 Interface Error Reporting Capabilities .................................... 152
Summary of SATA Interface Error Conditions........................................................ 152
Summary of SATA Interface Error Reporting Capabilities ........................................ 153
Summary of Serial I/O Interface Error Conditions.................................................. 153
Summary of Serial I/O Interface Error Reporting Capabilities .................................. 153
Summary of Memory Controller Error Conditions................................................... 154
Summary of Memory Controller Error Reporting Capabilities ................................... 155
Summary of Gigabit Ethernet MAC Error Conditions............................................... 156
Summary of Gigabit Ethernet MAC Error Reporting Capabilities ............................... 156
Summary of CAN Error Conditions....................................................................... 157
Summary of CAN Error Reporting Capabilities ....................................................... 157
Summary of SSP Error Conditions ....................................................................... 158
Summary of SSP Error Reporting Capabilities ....................................................... 158
Summary of Local Expansion Bus Error Conditions ................................................ 158
Summary of Local Expansion Bus Error Reporting Capabilities................................. 159
Types of Reset and Wake-up from Power Saving States ......................................... 161
Power Wells and External Voltages ...................................................................... 162
EP80579 Power Supply Pins ............................................................................... 168
Power Rail Sequence Signal Timings.................................................................... 171
Powergood Reset Timings .................................................................................. 173
Hard Reset Timings........................................................................................... 174
Global Power States .......................................................................................... 178
Device States................................................................................................... 178
Sleeping States ................................................................................................ 179
CPU States ...................................................................................................... 179
ACPI States ..................................................................................................... 180
Power Wells Status for Supported ACPI States* .................................................... 180
Definition of the Views Used in Register Description Tables..................................... 184
View Convention to Describe Single Versus Multiple Physical Registers ..................... 185
Offset Convention to Describe Multiple Physical Registers in the Same Device ........... 186
EG_SINGLE: Example Single Register with Different Views ..................................... 187
EG_MULTI_DIFF: Example Multiple Registers in Different Devices with Different
Views.............................................................................................................. 187
EG_MULTI_SAME[1-2]: Example Multiple Registers in Same Device with Different
Views.............................................................................................................. 188
EG_INDEX: Example Single Indexed Register ....................................................... 188
Register Field Access Attributes .......................................................................... 189
Bus 0, Device 0, Function 0: Summary of IMCH PCI Configuration Registers ............. 191
Bus 0, Device 0, Function 0: Summary of IMCH Configuration Registers Mapped Through
NSIBAR Memory BAR ........................................................................................ 192
Bus 0, Device 0, Function 0: Summary of IMCH SMRBASE Registers ........................ 193
Bus 0, Device 0, Function 1: Summary of IMCH Error Reporting PCI Configuration
Registers ......................................................................................................... 195
Bus 0, Device 1, Function 0: Summary of EDMA PCI Configuration Registers ............ 197
Intel^® EP80579 Integrated Processor Product Line Datasheet
56
August 2009
Order Number: 320066-003US