EP80579 Datasheet, PDF (1135/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
30.3.3
APIC Memory-Mapped Register Details
The APIC is accessed via an indirect addressing scheme. Two registers are visible by
software for manipulation of most of the APIC registers. These registers are mapped
into memory space. The registers are shown inTable 30-20.
Table 30-20. Summary of APIC Registers Mapped in Memory Space“
Offset Start Offset End
Register ID - Description
0000h (4B)
0010h (4B)
0040h (4B)
0000h (4B)
0010h (4B)
0040h (4B)
“APIC_IDX - Index Register” on page 1135
“APIC_DAT – Data Register” on page 1136
“APIC_EOI - EOI Register” on page 1136
Default
Value
00h
00h
00h
30.3.3.1
APIC_IDX - Index Register
The Index register selects which APIC indirect register to be manipulated by software.
The selector values for the indirect registers are listed in Table 30-21. Software
programs this register to select the desired APIC internal register.
Table 30-21. APIC_IDX - Index Register
Description:
View: IA F
Base Address: FEC00000h
Offset Start: 0000h (4B)
Offset End: 0000h (4B)
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
This is an 8-bit pointer into the I/O APIC indirect
APIC_Index register table listed in Section 30-20, “Summary of APIC
Registers Mapped in Memory Space“”.
Bit Reset
Value
00h
Bit Access
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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