EP80579 Datasheet, PDF (422/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-43. DRA[1:0] Field Selection
Case
1 DIMM, single
rank
1 DIMM, dual
rank
2 DIMMs, (one
rank each)
DRA0
[DTYPE_
MSB]
0 (single rank)
1 (dual rank)
1 (dual rank)
0 (single rank
per DIMM)
0 (single rank
per DIMM)
Address
any address up
to DRB0 limit
any address up
to DRB0 limit
any address
between DRB0
and DRB2 limit
any address up
to DRB0 limit
any address
between DRB0
and DRB2 limit
Value used for
DIMMTECH
Value used
for
num_column
/num_row
DRA0
[DIMMTECH_EV
EN]
DRA0
[DIMMTECH_EV
EN]
DRA0
[DIMMTECH_EV
EN]
DRA0
[DIMMTECH_EV
EN]
DRA1
[DIMMTECH_EV
EN]
DRA0
[NC_EVEN/
NR_EVEN]
DRA0
[NC_EVEN/
NR_EVEN]
DRA0
[NC_EVEN/
NR_EVEN]
DRA0
[NC_EVEN/
NR_EVEN]
DRA1
[NC_EVEN/
NR_EVEN]
Value used
for DW
DRA0
[DW_EVEN]
DRA0
[DW_EVEN]
DRA0
[DW_EVEN]
DRA0
[DW_EVEN]
DRA0
[DW_EVEN]
Value used for
DTYPE
DRA0
[DTYPE]
DRA0
[DTYPE]
DRA0
[DTYPE]
DRA0
[DTYPE]
DRA0
[DTYPE]
Table 16-44. Offset 70h: DRA[0-1] - DRAM Row [0:1] Attribute Register (Sheet 1 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 70h at 4h
Offset End: 73h at 4h
Size: 32 bit
Default: 00000515h
Power Well: Core
Bit Range
31 :29
28 :26
Bit Acronym
Bit Description
Sticky
Number of Rows for odd numbered row.
NR_ODD _{Functionality and encoding is exactly the same as}
N
NR_EVEN
Number of Columns for odd numbered row.
NC_ODD _{Functionality and encoding is exactly the same as}
N
NC_EVEN
Number of Rows for even numbered row: This information
is used by the Mbist engine.
Note that this field should be programmed to be consistent
with the DIMMTECH fields of the DRA register.
Bit Reset
Value
000b
000b
Bit Access
RW
RW
25 :23
NR_EVEN
000
001
010
011
Others
8192
16,384
32,768
65,536
Reserved
N
000b
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
422
August 2009
Order Number: 320066-003US