EP80579 Datasheet, PDF (869/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.3.4.4
Offset 12Ch: PxSCTL[0-1] – Port [0-1] Serial ATA Control Register
This is a 32-bit read-write register by which software controls SATA capabilities. Writes
to this register result in an action being taken by the host adapter or interface. Reads
from the register return the last value written to it.
Table 23-67. Offset 12Ch: PxSCTL[0-1] – Port [0-1] Serial ATA Control Register
Description:
View: PCI
BAR: ABAR
Bus:Device:Function: 0:31:2
Offset Start: 12Ch, 1ACh
Offset End: 12Fh, 1AFh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 20
19 : 16
15 : 12
11 : 08
07 : 04
03 : 00
Bit Acronym
Bit Description
Sticky
Reserved
Reserved
SPM
IPM
SPD
DET
Reserved
Reserved.
Select Power Management (SPM): This field is not
used by AHCI.
Interface Power Management Transitions Allowed
(IPM): Indicates which power states the HBA is allowed
to transition to. If an interface power management state is
not allowed via this register field, the HBA will not initiate
that state and the HBA will PMNAK_P any request from the
device to enter that state.
0h =No interface restrictions
1h =Transitions to the PARTIAL state disabled
2h =Transitions to the SLUMBER state disabled
3h =Transitions to both PARTIAL and SLUMBER states
disabled
All other values reserved
Speed Allowed (SPD): Indicates the highest allowable
speed of the interface. This speed is limited by the
HCAP.ISS field. For example, if HCAP.ISS is limited to
Gen1 speeds, only Gen1 speeds will be negotiated, even if
a 0h or 2h is programmed in this register.
0h =No speed negotiation restrictions
1h =Limit speed negotiation to Generation 1
communication rate
2h =Limit speed negotiation to Generation 2
communication rate
All other values reserved.
Device Detection Initialization (DET): Controls the
HBA’s device detection and interface initialization.
0h =No device detection or initialization action requested
1h =Perform interface communication initialization
sequence to establish communication. This is functionally
equivalent to a hard reset and results in the interface
being reset and communications reinitialized. While this
field is 1h, COMRESET is continuously transmitted on the
interface. Software should leave the DET field set to 1h for
a minimum of 1 millisecond to ensure that a COMRESET is
sent on the interface.
4h =Disable the Serial ATA interface and put Phy in offline
mode.
All other values reserved.
This field may only be changed to 1h or 4h when
PxCMD.ST is ‘0’. Changing this field to 1h or 4h while the
HBA is running results in undefined behavior.
Bit Reset
Value
0h
0h
0h
0h
0h
0h
Bit Access
RO
RW
RW
RW
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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