EP80579 Datasheet, PDF (596/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-217.Offset 160h: PEAFERR - PCI Express First Error Register (Sheet 2 of 2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 160h
Offset End: 163h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 160h
Offset End: 163h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
05
04
03
02
01
00
Bit Acronym
Bit Description
Sticky
USFED
Unit Specific Fatal Error Detected [STICKY]: This bit is
for fatal errors not in the PCI Express* specification as
logged by the PEAUNITERR register. The PEAMASKERR
register only prevents reporting of the unit errors, but does _Y
not prevent the logging of errors in this register.
0 = No error detected
1 = Error Detected
Unit Specific Non-Fatal Error Detected [STICKY]: This
bit is for non-fatal errors not in the PCI Express*
specification as logged by the PEAUNITERR register. The
PEAMASKERR register only prevents reporting of the unit
USNFED _{errors, but does not prevent the logging of errors in this}
Y
register.
0 = No error detected
1 = Error Detected
Unit Specific Correctable Error Detected [STICKY]:
This bit is for correctable errors not in the PCI Express*
specification as logged by the PEAUNITERR register. The
PEAMASKERR register only prevents reporting of the unit
USCED
errors, but does not prevent the logging of errors in this
Y
register.
0 = No error detected
1 = Error Detected
FEMR
Fatal Error Message Received [STICKY]: This bit is not
set for internally detected fatal errors a.k.a. virtual fatal
messages. These received fatal error messages can be
masked by the SERR enable bit in the Bridge Control
Y
Register, if the SERR enable bit is a 0.
0 = No ERR_FATAL message received
1 = An ERR_FATAL message is received.
Non-fatal Error Message Received [STICKY]: This bit
is not set for internally detected non-fatal errors a.k.a.
virtual non-fatal messages. These received non-fatal error
NFEMR
messages can be masked by the SERR enable bit in the
Y
Bridge Control Register, if the SERR enable bit is a 0.
0 = No ERR_NONFATAL message received
1 = An ERR_NONFATAL message is received.
Correctable Error Message Received [STICKY]: This
bit is not set for internally detected correctable errors
a.k.a. virtual correctable messages. These received
correctable error messages can be masked by the SERR
CEMR
enable bit in the Bridge Control Register, if the SERR
Y
enable bit is a 0.
0 = No ERR_COR message received
1 = An ERR_COR message is received.
Bit Reset
Value
0b
0b
0b
0b
0b
0b
Bit Access
RWC
RWC
RWC
RWC
RWC
RWC
Intel^® EP80579 Integrated Processor Product Line Datasheet
596
August 2009
Order Number: 320066-003US