EP80579 Datasheet, PDF (753/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
19.2.6.2
Offset D4h: FS2: FWH ID Select 2 Register
This register contains the additional IDSEL fields the LPC Bridge uses for memory
cycles going to the FWH.
Table 19-28. Offset D4h: FS2: FWH ID Select 2 Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:0
Offset Start: D4h
Offset End: D5h
Size: 16 bit
Default: 4567h
Power Well: Core
Bit Range
15 :12
11 :08
07 :04
03 :00
Bit Acronym
Bit Description
Sticky
70-7F IDSEL: Is used in FWH cycle for range enabled by
FDE.E70. Used for two, 1-M Firmware Hub memory
ranges.
I70
The IDSEL programmed in this field addresses the
following memory ranges:
FF70 0000h – FF7F FFFFh
FF30 0000h – FF3F FFFFh
60-6F IDSEL: Is used in FWH cycle for range enabled by
FDE.E60. Used for two, 1-M Firmware Hub memory
ranges.
I60
The IDSEL programmed in this field addresses the
following memory ranges:
FF60 0000h – FF6F FFFFh
FF20 0000h – FF2F FFFFh
50-5F IDSEL: Is used in FWH cycle for range enabled by
FDE.E50. Used for two, 1-M Firmware Hub memory
ranges.
I50
The IDSEL programmed in this field addresses the
following memory ranges:
FF50 0000h – FF5F FFFFh
FF10 0000h – FF1F FFFFh
40-4F IDSEL: Is used in FWH cycle for range enabled by
FDE.E40. Used for two, 1-M Firmware Hub memory
ranges.
I40
The IDSEL programmed in this field addresses the
following memory ranges:
FF40 0000h – FF4F FFFFh
FF00 0000h – FF0F FFFFh
Bit Reset
Value
4h
5h
6h
7h
Bit Access
RW
RW
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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