EP80579 Datasheet, PDF (78/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
35-87 Offset F1h: MCP: Message Signalled Interrupt Next Capability Pointer Register ..... 1288
35-88 Offset F2h: MCTL: Message Signalled Interrupt Control Register ......................... 1289
35-89 Offset F4h: MADR: Message Signalled Interrupt Address Register ........................ 1289
35-90 Offset F8h: MDATA: Message Signalled Interrupt Data Register ........................... 1290
35-91 Bus M, Device 6, Function 0: Summary of SSP Controller PCI
Configuration Registers ................................................................................... 1291
35-92 Offset 00h: VID: Vendor Identification Register ................................................. 1292
35-93 Offset 02h: DID: Device Identification Register ................................................. 1292
35-94 Offset 04h: PCICMD: Device Command Register ............................................... 1292
35-95 Offset 06h: PCISTS: PCI Device Status Register ................................................ 1293
35-96 Offset 08h: RID: Revision ID Register .............................................................. 1294
35-97 Offset 09h: CC: Class Code Register ................................................................ 1295
35-98 Offset 0Eh: HDR: Header Type Register ........................................................... 1295
35-99 Offset 10h: CSRBAR: Control and Status Registers Base Address Register ............ 1296
35-100 Offset 2Ch: SVID: Subsystem Vendor ID Register ............................................. 1296
35-101 Offset 2Eh: SID: Subsystem ID Register .......................................................... 1297
35-102 Offset 34h: CP: Capabilities Pointer Register ..................................................... 1297
35-103 Offset 3Ch: IRQL: Interrupt Line Register ......................................................... 1297
35-104 Offset 3Dh: IRQP: Interrupt Pin Register .......................................................... 1298
35-105 Offset DCh: PCID: Power Management Capability ID Register ............................. 1298
35-106 Offset DDh: PCP: Power Management Next Capability Pointer Register ................. 1299
35-107 Offset DEh: PMCAP: Power Management Capability Register ............................... 1299
35-108 Offset E0h: PMCS: Power Management Control and Status Register ..................... 1300
35-109 Offset E4h: SCID: Signal Target Capability ID Register ...................................... 1300
35-110 Offset E5h: SCP: Signal Target Next Capability Pointer Register .......................... 1301
35-111 Offset E6h: SBC: Signal Target Byte Count Register .......................................... 1301
35-112 Offset E7h: STYP: Signal Target Capability Type Register ................................... 1301
35-113 Offset E8h: SMIA: Signal Target IA Mask Register ............................................. 1302
35-114 Offset ECh: SINT: Signal Target Raw Interrupt Register ...................................... 1302
35-115 Offset F0h: MCID: Message Signalled Interrupt Capability ID Register .................. 1303
35-116 Offset F1h: MCP: Message Signalled Interrupt Next Capability Pointer Register ..... 1303
35-117 Offset F2h: MCTL: Message Signalled Interrupt Control Register ......................... 1303
35-118 Offset F4h: MADR: Message Signalled Interrupt Address Register ........................ 1304
35-119 Offset F8h: MDATA: Message Signalled Interrupt Data Register ........................... 1304
35-120 Bus M, Device 7, Function 0: Summary of IEEE 1588 Timestamp Unit PCI Configuration
Registers ....................................................................................................... 1305
35-121 Offset 00h: VID: Vendor Identification Register ................................................. 1306
35-122 Offset 02h: DID: Device Identification Register ................................................. 1306
35-123 Offset 04h: PCICMD: Device Command Register ............................................... 1306
35-124 Offset 06h: PCISTS: PCI Device Status Register ................................................ 1307
35-125 Offset 08h: RID: Revision ID Register .............................................................. 1308
35-126 Offset 09h: CC: Class Code Register ................................................................ 1308
35-127 Offset 0Eh: HDR: Header Type Register ........................................................... 1309
35-128 Offset 10h: CSRBAR: Control and Status Registers Base Address Register ............ 1309
35-129 Offset 2Ch: SVID: Subsystem Vendor ID Register ............................................. 1310
35-130 Offset 2Eh: SID: Subsystem ID Register .......................................................... 1310
35-131 Offset 34h: CP: Capabilities Pointer Register ..................................................... 1310
35-132 Offset 3Ch: IRQL: Interrupt Line Register ......................................................... 1311
35-133 Offset 3Dh: IRQP: Interrupt Pin Register .......................................................... 1311
35-134 Offset DCh: PCID: Power Management Capability ID Register ............................. 1312
35-135 Offset DDh: PCP: Power Management Next Capability Pointer Register ................. 1312
35-136 Offset DEh: PMCAP: Power Management Capability Register ............................... 1313
35-137 Offset E0h: PMCS: Power Management Control and Status Register ..................... 1313
35-138 Offset E4h: SCID: Signal Target Capability ID Register ...................................... 1314
35-139 Offset E5h: SCP: Signal Target Next Capability Pointer Register .......................... 1314
Intel^® EP80579 Integrated Processor Product Line Datasheet
78
August 2009
Order Number: 320066-003US